From: Mark Brown <broonie@opensource.wolfsonmicro.com>
Date: Sat, 10 Dec 2011 12:38:32 +0000 (+0800)
Subject: ASoC: Fix WM8996 24.576MHz clock operation
X-Git-Tag: upstream/snapshot3+hdmi~8480^2~5
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=37d5993c5cc9bc83762ae1b5bd287438022e8afe;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git

ASoC: Fix WM8996 24.576MHz clock operation

Record the clock after the divider as that is what all SYSCLK users see.
Without this the other clock configuration in the device comes out at
half rate.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@kernel.org
---

diff --git a/sound/soc/codecs/wm8996.c b/sound/soc/codecs/wm8996.c
index 645c980..a33b04d 100644
--- a/sound/soc/codecs/wm8996.c
+++ b/sound/soc/codecs/wm8996.c
@@ -1968,6 +1968,7 @@ static int wm8996_set_sysclk(struct snd_soc_dai *dai,
 		break;
 	case 24576000:
 		ratediv = WM8996_SYSCLK_DIV;
+		wm8996->sysclk /= 2;
 	case 12288000:
 		snd_soc_update_bits(codec, WM8996_AIF_RATE,
 				    WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);