From: Steve Ellcey <sje@cup.hp.com>
Date: Wed, 3 Oct 2012 21:11:46 +0000 (+0000)
Subject: 2012-10-04  Chao-ying Fu  <fu@mips.com>
X-Git-Tag: cygwin-1_7_17-release~61
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=37cb8f8e706d41879dfae054e577b4efa5ec1e28;p=external%2Fbinutils.git

2012-10-04  Chao-ying Fu  <fu@mips.com>
	    Steve Ellcey  <sellcey@mips.com>

	* mips/mips3264r2.igen (rdhwr): New.
---

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 95e23de..4d5bde2 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,8 @@
+2012-10-04  Chao-ying Fu  <fu@mips.com>
+	    Steve Ellcey  <sellcey@mips.com>
+
+	* mips/mips3264r2.igen (rdhwr): New.
+
 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
 
 	* configure.ac: Always link against dv-sockser.o.
diff --git a/sim/mips/mips3264r2.igen b/sim/mips/mips3264r2.igen
index c52ec3b..e0b6d5b 100644
--- a/sim/mips/mips3264r2.igen
+++ b/sim/mips/mips3264r2.igen
@@ -241,6 +241,17 @@
 }
 
 
+011111,00000,5.RT,5.RD,00000,111011::32::RDHWR
+"rdhwr r<RT>, r<RD>"
+*mips32r2:
+*mips64r2:
+{
+  // Return 0 for all hardware registers currently
+  GPR[RT] = EXTEND32 (0);
+  TRACE_ALU_RESULT1 (GPR[RT]);
+}
+
+
 011111,00000,5.RT,5.RD,00010,100000::32::WSBH
 "wsbh r<RD>, r<RT>"
 *mips32r2: