From: Martin Blumenstingl Date: Sun, 2 Dec 2018 21:42:18 +0000 (+0100) Subject: clk: meson: meson8b: fix the offset of vid_pll_dco's N value X-Git-Tag: v5.4-rc1~1882^2~7^5^2~4 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=376d8c45bd6ac79f02ecf9ca1606dc5d1b271bc0;p=platform%2Fkernel%2Flinux-rpi.git clk: meson: meson8b: fix the offset of vid_pll_dco's N value Unlike the other PLLs on Meson8b the N value "vid_pll_dco" (a better name would be hdmi_pll_dco or - as the datasheet calls it - HPLL) is located at HHI_VID_PLL_CNTL[14:10] instead of [13:9]. This results in an incorrect calculation of the rate of this PLL because the value seen by the kernel is double the actual N (divider) value. Update the offset of the N value to fix the calculation of the PLL rate. Fixes: 28b9fcd016126e ("clk: meson8b: Add support for Meson8b clocks") Reported-by: Jianxin Pan Signed-off-by: Martin Blumenstingl Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20181202214220.7715-2-martin.blumenstingl@googlemail.com --- diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index f906a9f..a4ae9c9 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -134,7 +134,7 @@ static struct clk_regmap meson8b_vid_pll_dco = { }, .n = { .reg_off = HHI_VID_PLL_CNTL, - .shift = 9, + .shift = 10, .width = 5, }, .l = {