From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Date: Tue, 10 Aug 2021 03:26:35 +0000 (+0800)
Subject: arm: socfpga: Changed misc_s10.c to misc_soc64.c
X-Git-Tag: v2021.10~42^2~7
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=37529cf2852a12424bfbbeb98be000116d747796;p=platform%2Fkernel%2Fu-boot.git

arm: socfpga: Changed misc_s10.c to misc_soc64.c

Rename to common file name to used by all SOC64 devices.
No functionality change.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 5779c55621..58afde950f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,7 +32,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
 obj-y	+= lowlevel_init_soc64.o
 obj-y	+= mailbox_s10.o
-obj-y	+= misc_s10.o
+obj-y	+= misc_soc64.o
 obj-y	+= mmu-arm64_s10.o
 obj-y	+= reset_manager_s10.o
 obj-y	+= system_manager_soc64.o
@@ -45,7 +45,7 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX
 obj-y	+= clock_manager_agilex.o
 obj-y	+= lowlevel_init_soc64.o
 obj-y	+= mailbox_s10.o
-obj-y	+= misc_s10.o
+obj-y	+= misc_soc64.o
 obj-y	+= mmu-arm64_s10.o
 obj-y	+= reset_manager_s10.o
 obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)	+= secure_vab.o
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
deleted file mode 100644
index 50c7f19ae1..0000000000
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ /dev/null
@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
- *
- */
-
-#include <altera.h>
-#include <common.h>
-#include <env.h>
-#include <errno.h>
-#include <init.h>
-#include <log.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/mailbox_s10.h>
-#include <asm/arch/misc.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/arch/system_manager.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * FPGA programming support for SoC FPGA Stratix 10
- */
-static Altera_desc altera_fpga[] = {
-	{
-		/* Family */
-		Intel_FPGA_SDM_Mailbox,
-		/* Interface type */
-		secure_device_manager_mailbox,
-		/* No limitation as additional data will be ignored */
-		-1,
-		/* No device function table */
-		NULL,
-		/* Base interface address specified in driver */
-		NULL,
-		/* No cookie implementation */
-		0
-	},
-};
-
-
-/*
- * Print CPU information
- */
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	puts("CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_ARCH_MISC_INIT
-int arch_misc_init(void)
-{
-	char qspi_string[13];
-
-	sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
-	env_set("qspi_clock", qspi_string);
-
-	return 0;
-}
-#endif
-
-int arch_early_init_r(void)
-{
-	socfpga_fpga_add(&altera_fpga[0]);
-
-	return 0;
-}
-
-/* Return 1 if FPGA is ready otherwise return 0 */
-int is_fpga_config_ready(void)
-{
-	return (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGA_CONFIG) &
-		SYSMGR_FPGACONFIG_READY_MASK) == SYSMGR_FPGACONFIG_READY_MASK;
-}
-
-void do_bridge_reset(int enable, unsigned int mask)
-{
-	/* Check FPGA status before bridge enable */
-	if (!is_fpga_config_ready()) {
-		puts("FPGA not ready. Bridge reset aborted!\n");
-		return;
-	}
-
-	socfpga_bridges_reset(enable);
-}
diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c
new file mode 100644
index 0000000000..7b973a79e8
--- /dev/null
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <altera.h>
+#include <common.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/io.h>
+#include <asm/global_data.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <log.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * FPGA programming support for SoC FPGA Stratix 10
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Intel_FPGA_SDM_Mailbox,
+		/* Interface type */
+		secure_device_manager_mailbox,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+
+
+/*
+ * Print CPU information
+ */
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	puts("CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+	char qspi_string[13];
+
+	sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
+	env_set("qspi_clock", qspi_string);
+
+	return 0;
+}
+#endif
+
+int arch_early_init_r(void)
+{
+	socfpga_fpga_add(&altera_fpga[0]);
+
+	return 0;
+}
+
+/* Return 1 if FPGA is ready otherwise return 0 */
+int is_fpga_config_ready(void)
+{
+	return (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGA_CONFIG) &
+		SYSMGR_FPGACONFIG_READY_MASK) == SYSMGR_FPGACONFIG_READY_MASK;
+}
+
+void do_bridge_reset(int enable, unsigned int mask)
+{
+	/* Check FPGA status before bridge enable */
+	if (!is_fpga_config_ready()) {
+		puts("FPGA not ready. Bridge reset aborted!\n");
+		return;
+	}
+
+	socfpga_bridges_reset(enable);
+}