From: Emma Anholt <emma@anholt.net>
Date: Wed, 3 Aug 2022 23:33:28 +0000 (-0700)
Subject: tu: Only emit as many VPC interp/repl regs as will be referenced.
X-Git-Tag: upstream/22.3.5~4423
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=374d1ce4915fdaf2725892ffe1c69d97ef2d3b3a;p=platform%2Fupstream%2Fmesa.git

tu: Only emit as many VPC interp/repl regs as will be referenced.

Saves a bit of CP overhead on pipeline switch.  Improves zink drawoverhead
-test 7 (shader program change) throughput by 1.10825% +/- 0.131485%
(n=10).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17932>
---

diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 699d8c7..079eca2 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -1394,6 +1394,7 @@ tu6_emit_vpc_varying_modes(struct tu_cs *cs,
 {
    uint32_t interp_modes[8] = { 0 };
    uint32_t ps_repl_modes[8] = { 0 };
+   uint32_t interp_regs = 0;
 
    if (fs) {
       for (int i = -1;
@@ -1418,14 +1419,17 @@ tu6_emit_vpc_varying_modes(struct tu_cs *cs,
             interp_modes[n] |= interp_mode >> shift;
             ps_repl_modes[n] |= ps_repl_mode >> shift;
          }
+         interp_regs = MAX2(interp_regs, n + 1);
       }
    }
 
-   tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
-   tu_cs_emit_array(cs, interp_modes, 8);
+   if (interp_regs) {
+      tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), interp_regs);
+      tu_cs_emit_array(cs, interp_modes, interp_regs);
 
-   tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
-   tu_cs_emit_array(cs, ps_repl_modes, 8);
+      tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), interp_regs);
+      tu_cs_emit_array(cs, ps_repl_modes, interp_regs);
+   }
 }
 
 void