From: Francisco Jerez Date: Fri, 14 Nov 2014 18:30:46 +0000 (+0200) Subject: i965: Don't tile 1D miptrees. X-Git-Tag: upstream/17.1.0~20902 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=36a17f0f991323410778392bc2d00f9d911d501b;p=platform%2Fupstream%2Fmesa.git i965: Don't tile 1D miptrees. It doesn't really improve locality of texture fetches, quite the opposite it's a waste of memory bandwidth and space due to tile alignment. v2: Check mt->logical_height0 instead of mt->target (Ken). Add short comment explaining why they shouldn't be tiled. Reviewed-by: Neil Roberts Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 64752dd..0e3888f 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -488,6 +488,13 @@ intel_miptree_choose_tiling(struct brw_context *brw, base_format == GL_DEPTH_STENCIL_EXT) return I915_TILING_Y; + /* 1D textures (and 1D array textures) don't get any benefit from tiling, + * in fact it leads to a less efficient use of memory space and bandwidth + * due to tile alignment. + */ + if (mt->logical_height0 == 1) + return I915_TILING_NONE; + int minimum_pitch = mt->total_width * mt->cpp; /* If the width is much smaller than a tile, don't bother tiling. */