From: Howard Chu <hyc@symas.com>
Date: Sun, 27 Jul 2014 01:16:02 +0000 (-0700)
Subject: Fix MIPS cache coherency on Linux
X-Git-Tag: accepted/tizen/5.0/unified/20181102.030725~332
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3630066843b7ca6b2cd12911d3e2fe3314cd4549;p=platform%2Fupstream%2Flmdb.git

Fix MIPS cache coherency on Linux

MIPS chips require manual control of on-chip caches. The cacheflush
syscall being used here only exists on MIPS Linux, other OSs will
require revisiting.
---

diff --git a/libraries/liblmdb/mdb.c b/libraries/liblmdb/mdb.c
index 84477c4..e1d7748 100644
--- a/libraries/liblmdb/mdb.c
+++ b/libraries/liblmdb/mdb.c
@@ -70,6 +70,15 @@
 #include <fcntl.h>
 #endif
 
+#if defined(__mips) && defined(__linux)
+/* MIPS has cache coherency issues, requires explicit cache control */
+#include <asm/cachectl.h>
+extern int cacheflush(char *addr, int nbytes, int cache);
+#define CACHEFLUSH(addr, bytes, cache)	cacheflush(addr, bytes, cache)
+#else
+#define CACHEFLUSH(addr, bytes, cache)
+#endif
+
 #include <errno.h>
 #include <limits.h>
 #include <stddef.h>
@@ -3581,6 +3590,11 @@ done:
 	if (env->me_txns)
 		env->me_txns->mti_txnid = txn->mt_txnid;
 
+	/* MIPS has cache coherency issues, this is a no-op everywhere else */
+	if (!(env->me_flags & MDB_WRITEMAP)) {
+		CACHEFLUSH(env->me_map, txn->mt_next_pgno * env->me_psize, DCACHE);
+	}
+
 	return MDB_SUCCESS;
 }