From: Oscar Mateo Date: Tue, 8 May 2018 21:29:32 +0000 (-0700) Subject: drm/i915/icl: Wa_1406680159 X-Git-Tag: v4.19~298^2~46^2~143 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=36204d80bacb5382c7944fceb14975c727def102;p=platform%2Fkernel%2Flinux-rpi.git drm/i915/icl: Wa_1406680159 Disable GWL clock gating to prevent an issue that might cause hangs. v2: Rebased on top of the WA refactoring v3: Wa_2201832410 officially merged with Wa_1406680159 v4: Added References (Mika) v5: - Rebased - C, not lisp (Chris) - Add reference where WA is better explained (Rodrigo) - Add reference to WA that got merged with this References: HSDES#1406681710 References: HSDES#1406680159 References: HSDES#2201832410 Signed-off-by: Oscar Mateo Cc: Mika Kuoppala Reviewed-by: Rodrigo Vivi Signed-off-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-11-git-send-email-oscar.mateo@intel.com --- diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 469a83d..a3fa01a 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -745,6 +745,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, I915_READ(SLICE_UNIT_LEVEL_CLKGATE) | MSCUNIT_CLKGATE_DIS); + + /* Wa_1406680159:icl */ + I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, + I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) | + GWUNIT_CLKGATE_DIS); } void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)