From: Ley Foon Tan <ley.foon.tan@intel.com>
Date: Fri, 10 Jul 2020 12:55:20 +0000 (+0800)
Subject: clk: agilex: Add NAND clock support
X-Git-Tag: v2021.10~486^2~29
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=36162a8eb8962e9447e9ad03b5103a3a66228476;p=platform%2Fkernel%2Fu-boot.git

clk: agilex: Add NAND clock support

Add get nand_clk and nand_x clock support.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---

diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
index 9927ada..d740299 100644
--- a/drivers/clk/altera/clk-agilex.c
+++ b/drivers/clk/altera/clk-agilex.c
@@ -533,7 +533,10 @@ static ulong socfpga_clk_get_rate(struct clk *clk)
 	case AGILEX_EMAC2_CLK:
 		return clk_get_emac_clk_hz(plat, clk->id);
 	case AGILEX_USB_CLK:
+	case AGILEX_NAND_X_CLK:
 		return clk_get_l4_mp_clk_hz(plat);
+	case AGILEX_NAND_CLK:
+		return clk_get_l4_mp_clk_hz(plat) / 4;
 	default:
 		return -ENXIO;
 	}