From: Anusha Srivatsa Date: Wed, 31 Oct 2018 00:19:17 +0000 (-0700) Subject: drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming X-Git-Tag: v5.4-rc1~1388^2~28^2~376 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=35b876db4a425e58d7fe63eb363bbfa50b8e4e74;p=platform%2Fkernel%2Flinux-rpi.git drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Add the newly added slice_row_per_frame parameter in the Picture Parameter Set registers. This defines the number of vertically stacked slices in a frame. Credits to Manasi for noticing bSpec change. Suggested-by: Manasi Navare Cc: Manasi Navare Signed-off-by: Anusha Srivatsa Reviewed-by: Manasi Navare Link: https://patchwork.freedesktop.org/patch/msgid/20181031001923.31442-1-manasi.d.navare@intel.com --- diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8d089ef..55d32ca 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10977,6 +10977,7 @@ enum skl_power_gate { #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) +#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)