From: Marc Zyngier Date: Tue, 5 Apr 2022 18:23:24 +0000 (+0100) Subject: irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES} X-Git-Tag: v6.1-rc5~1070^2~43^2~3^2~3 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=34453c2e9f799d02f5f379519495208bbd96a935;p=platform%2Fkernel%2Flinux-starfive.git irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES} As we're about to expose GICR_CTLR.{IR,CES} to guests, populate the include file with the architectural values. Signed-off-by: Marc Zyngier Reviewed-by: Oliver Upton Link: https://lore.kernel.org/r/20220405182327.205520-2-maz@kernel.org --- diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 12d91f0..7286913 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -127,6 +127,8 @@ #define GICR_PIDR2 GICD_PIDR2 #define GICR_CTLR_ENABLE_LPIS (1UL << 0) +#define GICR_CTLR_CES (1UL << 1) +#define GICR_CTLR_IR (1UL << 2) #define GICR_CTLR_RWP (1UL << 3) #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)