From: Tom Stellard <tstellar@redhat.com>
Date: Wed, 26 Sep 2018 16:53:36 +0000 (+0000)
Subject: AMDGPU/SI: Change predicate to isCIOnly for 32-bit imm s_buffer_load* patterns
X-Git-Tag: llvmorg-8.0.0-rc1~7860
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=344475fce536e2f2f88d5e3b0a7bde51a2149341;p=platform%2Fupstream%2Fllvm.git

AMDGPU/SI: Change predicate to isCIOnly for 32-bit imm s_buffer_load* patterns

Summary:
This is essentially NFC, because the complex pattern used for these patterns
will fail on non-CI, but this makes the pattern consistent with other CI
smrd patterns.  It is also a performance improvement, because the pattern
will now fail earlier on non-CI.

Reviewers: arsenm, nhaehnle

Reviewed By: arsenm

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D52469

llvm-svn: 343125
---

diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index bd983cd6f190..6037dcc0e793 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -777,7 +777,7 @@ def : SMRD_Pattern_ci <"S_LOAD_DWORDX16", v16i32>;
 class SMLoad_Pattern_ci <string Instr, ValueType vt> : GCNPat <
   (vt (SIsbuffer_load v4i32:$sbase, (SMRDBufferImm32 i32:$offset), i1:$glc)),
   (!cast<InstSI>(Instr) $sbase, $offset, (as_i1imm $glc))> {
-  let OtherPredicates = [isCI]; // should this be isCIOnly?
+  let OtherPredicates = [isCIOnly];
 }
 
 def : SMLoad_Pattern_ci <"S_BUFFER_LOAD_DWORD_IMM_ci", i32>;