From: Andrey Belevantsev Date: Mon, 9 Apr 2018 09:08:28 +0000 (+0300) Subject: re PR rtl-optimization/83530 (ICE in reset_sched_cycles_in_current_ebb, at sel-sched... X-Git-Tag: upstream/12.2.0~32435 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=33bacbcba534374b3e2c7693ae9147b96540f43f;p=platform%2Fupstream%2Fgcc.git re PR rtl-optimization/83530 (ICE in reset_sched_cycles_in_current_ebb, at sel-sched.c:7150) PR rtl-optimization/83530 * sel-sched.c (force_next_insn): New global variable. (remove_insn_for_debug): When force_next_insn is true, also leave only next insn in the ready list. (sel_sched_region): When the region wasn't scheduled, make another pass over it with force_next_insn set to 1. * gcc.dg/pr83530.c: New test. From-SVN: r259228 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2bffb97..a09b7ba 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2018-04-09 Andrey Belevantsev + + PR rtl-optimization/83530 + + * sel-sched.c (force_next_insn): New global variable. + (remove_insn_for_debug): When force_next_insn is true, also leave only + next insn in the ready list. + (sel_sched_region): When the region wasn't scheduled, make another pass + over it with force_next_insn set to 1. + 2018-04-08 Monk Chiang * config.gcc (nds32le-*-*, nds32be-*-*): Add nds32/nds32_intrinsic.h diff --git a/gcc/sel-sched.c b/gcc/sel-sched.c index 76092f9..cd29df3 100644 --- a/gcc/sel-sched.c +++ b/gcc/sel-sched.c @@ -5004,12 +5004,16 @@ remove_temp_moveop_nops (bool full_tidying) distinguishing between bookkeeping copies and original insns. */ static int max_uid_before_move_op = 0; +/* When true, we're always scheduling next insn on the already scheduled code + to get the right insn data for the following bundling or other passes. */ +static int force_next_insn = 0; + /* Remove from AV_VLIW_P all instructions but next when debug counter tells us so. Next instruction is fetched from BNDS. */ static void remove_insns_for_debug (blist_t bnds, av_set_t *av_vliw_p) { - if (! dbg_cnt (sel_sched_insn_cnt)) + if (! dbg_cnt (sel_sched_insn_cnt) || force_next_insn) /* Leave only the next insn in av_vliw. */ { av_set_iterator av_it; @@ -7641,9 +7645,15 @@ sel_sched_region (int rgn) if (schedule_p) sel_sched_region_1 (); else - /* Force initialization of INSN_SCHED_CYCLEs for correct bundling. */ - reset_sched_cycles_p = true; - + { + /* Schedule always selecting the next insn to make the correct data + for bundling or other later passes. */ + pipelining_p = false; + force_next_insn = 1; + sel_sched_region_1 (); + force_next_insn = 0; + } + reset_sched_cycles_p = pipelining_p; sel_region_finish (reset_sched_cycles_p); } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 08a80f1..c1653f7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-04-09 Andrey Belevantsev + + PR rtl-optimization/83530 + * gcc.dg/pr83530.c: New test. + 2018-04-07 Thomas Koenig PR middle-end/82976 diff --git a/gcc/testsuite/gcc.dg/pr83530.c b/gcc/testsuite/gcc.dg/pr83530.c new file mode 100644 index 0000000..f4d8927 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr83530.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } */ +/* { dg-options "-O2 -fmodulo-sched -fselective-scheduling2" } */ +int vm, z0; +short int mz; + +int +ny (void) +{ + int ch; + + for (ch = 0; ch < 6; ++ch) + vm += ch / vm; + + return z0 + mz; +}