From: Alex Deucher Date: Wed, 3 Jul 2013 19:14:25 +0000 (-0400) Subject: drm/radeon/sumo: implement support for disable_gfx_power_gating_in_uvd flag X-Git-Tag: v3.12-rc1~464^2~17^2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=338a95a95508537e23c82d59a2d87be6fde4b6ff;p=kernel%2Fkernel-generic.git drm/radeon/sumo: implement support for disable_gfx_power_gating_in_uvd flag Some asic revisions need to disable PG when UVD is active. Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c index b13448f..dc59906 100644 --- a/drivers/gpu/drm/radeon/sumo_dpm.c +++ b/drivers/gpu/drm/radeon/sumo_dpm.c @@ -824,7 +824,9 @@ static void sumo_setup_uvd_clocks(struct radeon_device *rdev, radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); if (pi->enable_gfx_power_gating) { - sumo_gfx_powergating_enable(rdev, true); + if (!pi->disable_gfx_power_gating_in_uvd || + !r600_is_uvd_state(new_rps->class, new_rps->class2)) + sumo_gfx_powergating_enable(rdev, true); } }