From: Yvan Roux Date: Wed, 15 Jun 2016 08:42:05 +0000 (+0200) Subject: Merge branches/gcc-6-branch rev 237469. X-Git-Tag: upstream/6.1~4 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=336d434c49ee9e0c0ea775026ca98f1906cf80e3;p=platform%2Fupstream%2Flinaro-gcc.git Merge branches/gcc-6-branch rev 237469. Change-Id: I4891542fc1d8fd3bb75e92a8805a8d069022b522 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0962f97..a44905c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,1064 @@ +2016-06-14 Jakub Jelinek + + Backported from mainline + 2016-06-10 Jakub Jelinek + + PR middle-end/71494 + * tree-nested.c (convert_nonlocal_reference_stmt): For GIMPLE_GOTO + without LABEL_DECL, set *handled_ops_p to false instead of true. + + 2016-06-08 Jakub Jelinek + Richard Biener + + PR c++/71448 + * fold-const.c (fold_comparison): Handle CONSTANT_CLASS_P (base0) + the same as DECL_P (base0) for indirect_base0. Use equality_code + in one further place. + + 2016-06-04 Jakub Jelinek + + PR tree-optimization/71405 + * tree-ssa.c (execute_update_addresses_taken): For clobber with + incompatible type, build a new clobber with the right type instead + of building a VIEW_CONVERT_EXPR around it. + +2016-06-13 Eric Botcazou + + * tree-ssa-sccvn.c (vn_reference_lookup_3): Use a uniform test and + update shared_lookup_references only once after changing operands. + +2016-06-13 Richard Biener + + PR tree-optimization/71505 + * tree-vect-data-refs.c (vect_analyze_data_ref_accesses): Make + assert match comment. + +2016-06-13 Andreas Krebbel + + Backport from mainline + 2016-06-13 Andreas Krebbel + + PR target/71379 + * config/s390/s390.c (s390_expand_builtin): Increase MAX_ARGS by + one. + +2016-06-10 Thomas Schwinge + + PR middle-end/71373 + Backport from trunk r237291: + * tree-nested.c (convert_nonlocal_omp_clauses) + (convert_local_omp_clauses): Handle OMP_CLAUSE_ASYNC, + OMP_CLAUSE_WAIT, OMP_CLAUSE_INDEPENDENT, OMP_CLAUSE_AUTO, + OMP_CLAUSE__CACHE_, OMP_CLAUSE_TILE. + + Backport from trunk r237291: + * gimplify.c (gimplify_adjust_omp_clauses): Discard + OMP_CLAUSE_TILE. + * omp-low.c (scan_sharing_clauses): Don't expect OMP_CLAUSE_TILE. + + Backport from trunk r237290: + * omp-low.c (scan_sharing_clauses): Don't expect + OMP_CLAUSE__CACHE_. + + Backport trunk r235964: + 2016-05-06 Nathan Sidwell + + * gimple.c (gimple_call_same_target_p): Unique functions are eq. + * tree-ssa-tail-merge.c (same_succ::equal): Check pointer eq + equality first. + +2016-06-09 Michael Meissner + + Back port from trunk + 2016-05-31 Michael Meissner + + * config/rs6000/vsx.md (vsx_splat_, V2DI/V2DF): Simplify + alternatives, eliminating preferred register class. Add support + for the MTVSRDD instruction in ISA 3.0. + (vsx_splat_v4si_internal): Use splat_input_operand instead of + reg_or_indexed_operand. + (vsx_splat_v4sf_internal): Likewise. + + Back port from trunk + 2016-05-31 Michael Meissner + + PR target/71186 + * config/rs6000/vsx.md (xxspltib__nosplit): Add alternatives + for loading up all 0's or all 1's. + + Back port from trunk + 2016-05-18 Michael Meissner + + PR target/70915 + * config/rs6000/constraints.md (wE constraint): New constraint + for a vector constant that can be loaded with XXSPLTIB. + (wM constraint): New constraint for a vector constant of a 1's. + (wS constraint): New constraint for a vector constant that can be + loaded with XXSPLTIB and a vector sign extend instruction. + * config/rs6000/predicates.md (xxspltib_constant_split): New + predicates for wE/wS constraints. + (xxspltib_constant_nosplit): Likewise. + (easy_vector_constant): Add support for constants that can be + loaded via XXSPLTIB. + (splat_input_operand): Add support for ISA 3.0 word splat operations. + * config/rs6000/rs6000.c (xxspltib_constant_p): New function to + return if a constant can be loaded with the ISA 3.0 XXSPLTIB + instruction and possibly with a sign extension. + (output_vec_const_move): Add support for XXSPLTIB. If we are + loading up 0/-1 into Altivec registers, prefer using VSPLTISW + instead of XXLXOR/XXLORC. + (rs6000_expand_vector_init): Add support for ISA 3.0 word splat + operations. + (rs6000_legitimize_reload_address): Likewise. + (rs6000_output_move_128bit): Use output_vec_const_move to emit + constants. + * config/rs6000/vsx.md (VSX_M): Add TImode (if -mvsx-timode) and + combine VSX_M and VSX_M2 into one iterator. + (VSX_M2): Likewise. + (VSINT_84): New iterators for loading constants with XXSPLTIB. + (VSINT_842): Likewise. + (UNSPEC_VSX_SIGN_EXTEND): New UNSPEC. + (xxspltib_v16qi): New insns to load up constants with the ISA 3.0 + XXSPLTIB instruction. + (xxspltib__nosplit): Likewise. + (xxspltib__split): New insn to load up constants with + XXSPLTIB and a sign extend instruction. + (vsx_mov): Replace single move that handled all vector types + with separate 32-bit and 64-bit moves. Combine the movti_ + moves (when -mvsx-timode is in effect) into the main vector + moves. Eliminate separate moves for , where the + preferred register class () is listed first, and the + secondary register class () is listed second with a '?' to + discourage use. Prefer loading 0/-1 in any VSX register for ISA + 3.0, and Altivec registers for ISA 2.06/2.07 (PR target/70915) so + that if the register was involved in a slow operation, the + clear/set operation does not wait for the slow operation to + finish. Adjust the length attributes for 32-bit mode. Use + rs6000_output_move_128bit and drop the use of the string + instructions for 32-bit movti when -mvsx-timode is in effect. Use + spacing so that the alternatives and attributes don't generate + long lines, and put things in columns, so that it is easier to + match up the operands and attributes with the insn alternatives. + (vsx_mov_64bit): Likewise. + (vsx_mov_32bit): Likewise. + (vsx_movti_64bit): Fold movti into normal vector moves. + (vsx_movti_32bit): Likewise. + (vsx_splat_, V4SI/V4SF modes): Add support for ISA 3.0 word + splat instructions. + (vsx_splat_v4si_internal): Likewise. + (vsx_splat_v4sf_internal): Likewise. + (vector fusion peepholes): Use VSX_M instead of VSX_M2. + (vsx_sign_extend_qi_): New ISA 3.0 instructions to sign + extend vector elements. + (vsx_sign_extend_hi_): Likewise. + (vsx_sign_extend_si_v2di): Likewise. + * config/rs6000/rs6000-protos.h (xxspltib_constant_p): Add + declaration. + * doc/md.texi (PowerPC constraints): Document the wE, wM, and wS + constraints. Add trailing period to wL documentation. + +2016-06-08 Jose E. Marchesi + + Backport from mainline + 2016-06-08 Jose E. Marchesi + + * config/sparc/driver-sparc.c (cpu_names): Fix the entry for the + SPARC-M7 and add an entry for SPARC-S7 cpus (Sonoma). + +2016-06-08 Eric Botcazou + + Backport from mainline + 2016-06-06 Jose E. Marchesi + + * config/sparc/sparc.md (cpu): Add niagara7 cpu type. + Include the M7 SPARC DFA scheduler. + New attribute v3pipe. + Annotate insns with v3pipe where appropriate. + Define cpu_feature vis4. + Add lzd instruction type and set it on clzdi_sp64 and clzsi_sp64. + Add (V8QI "8") to vbits. + Add insns {add,sub}v8qi3 + Add insns ss{add,sub}v8qi3 + Add insns us{add,sub}{v8qi,v4hi}3 + Add insns {min,max}{v8qi,v4hi,v2si}3 + Add insns {minu,maxu}{v8qi,v4hi,v2si}3 + Add insns fpcmp{le,gt,ule,ug,ule,ugt}{8,16,32}_vis. + * config/sparc/niagara4.md: Add a comment explaining the + discrepancy between the documented latenty numbers and the + implemented ones. + * config/sparc/niagara7.md: New file. + * configure.ac (HAVE_AS_SPARC5_VIS4): Define if the assembler + supports SPARC5 and VIS 4.0 instructions. + * configure: Regenerate. + * config.in: Likewise. + * config.gcc: niagara7 is a supported cpu in sparc*-*-* targets. + * config/sparc/sol2.h (ASM_CPU32_DEFAUILT_SPEC): Set for + TARGET_CPU_niagara7. + (ASM_CPU64_DEFAULT_SPEC): Likewise. + (CPP_CPU_SPEC): Handle niagara7. + (ASM_CPU_SPEC): Likewise. + * config/sparc/sparc-opts.h (processor_type): Add + PROCESSOR_NIAGARA7. + (mvis4): New option. + * config/sparc/sparc.h (TARGET_CPU_niagara7): Define. + (AS_NIAGARA7_FLAG): Define. + (ASM_CPU64_DEFAULT_SPEC): Set for niagara7. + (CPP_CPU64_DEFAULT_SPEC): Likewise. + (CPP_CPU_SPEC): Handle niagara7. + (ASM_CPU_SPEC): Likewise. + * config/sparc/sparc.c (niagara7_costs): Define. + (sparc_option_override): Handle niagara7 and adjust cache-related + parameters with better values for niagara cpus. Also support VIS4. + (sparc32_initialize_trampoline): Likewise. + (sparc_use_sched_lookahead): Likewise. + (sparc_issue_rate): Likewise. + (sparc_register_move_cost): Likewise. + (dump_target_flag_bits): Support VIS4. + (sparc_vis_init_builtins): Likewise. + (sparc_builtins): Likewise. + * config/sparc/sparc-c.c (sparc_target_macros): Define __VIS__ for + VIS4 4.0. + * config/sparc/driver-sparc.c (cpu_names): Add SPARC-M7 and + UltraSparc M7. + * config/sparc/sparc.opt (sparc_processor_type): New value + niagara7. + * config/sparc/visintrin.h (__attribute__): Prototypes for the + VIS4 builtins. + * doc/invoke.texi (SPARC Options): Document -mcpu=niagara7 and + -mvis4. + * doc/extend.texi (SPARC VIS Built-in Functions): Document the + VIS4 builtins. + + 2016-05-30 Jose E. Marchesi + + * config.gcc (sparc*-*-*): Support cpu_32, cpu_64, tune_32 and + tune_64. + * doc/install.texi (--with-cpu-32, --with-cpu-64): Document + support on SPARC. + * config/sparc/linux64.h (OPTION_DEFAULT_SPECS): Add entries for + cpu_32, cpu_64, tune_32 and tune_64. + * config/sparc/sol2.h (OPTION_DEFAULT_SPECS): Likewise. + +2016-06-08 Ilya Verbin + + Backport from mainline + 2016-05-25 Ilya Verbin + + * config/i386/i386-builtin-types.def: Add V16SI_FTYPE_V16SF, + V8DF_FTYPE_V8DF_ROUND, V16SF_FTYPE_V16SF_ROUND, V16SI_FTYPE_V16SF_ROUND. + * config/i386/i386.c (enum ix86_builtins): Add + IX86_BUILTIN_CVTPS2DQ512_MASK, IX86_BUILTIN_FLOORPS512, + IX86_BUILTIN_FLOORPD512, IX86_BUILTIN_CEILPS512, IX86_BUILTIN_CEILPD512, + IX86_BUILTIN_TRUNCPS512, IX86_BUILTIN_TRUNCPD512, + IX86_BUILTIN_CVTPS2DQ512, IX86_BUILTIN_VEC_PACK_SFIX512, + IX86_BUILTIN_FLOORPS_SFIX512, IX86_BUILTIN_CEILPS_SFIX512, + IX86_BUILTIN_ROUNDPS_AZ_SFIX512. + (builtin_description bdesc_args): Add __builtin_ia32_floorps512, + __builtin_ia32_ceilps512, __builtin_ia32_truncps512, + __builtin_ia32_floorpd512, __builtin_ia32_ceilpd512, + __builtin_ia32_truncpd512, __builtin_ia32_cvtps2dq512, + __builtin_ia32_vec_pack_sfix512, __builtin_ia32_roundps_az_sfix512, + __builtin_ia32_floorps_sfix512, __builtin_ia32_ceilps_sfix512. + Change IX86_BUILTIN_CVTPS2DQ512 to IX86_BUILTIN_CVTPS2DQ512_MASK for + __builtin_ia32_cvtps2dq512_mask. + (ix86_expand_args_builtin): Handle V8DF_FTYPE_V8DF_ROUND, + V16SF_FTYPE_V16SF_ROUND, V16SI_FTYPE_V16SF_ROUND, V16SI_FTYPE_V16SF. + (ix86_builtin_vectorized_function): Handle builtins mentioned above. + * config/i386/sse.md + (avx512f_fix_notruncv16sfv16si): + Rename to ... + (avx512f_fix_notruncv16sfv16si): ... this. + (avx512f_cvtpd2dq512): Rename + to ... + (avx512f_cvtpd2dq512): ... this. + (avx512f_vec_pack_sfix_v8df): New define_expand. + (avx512f_roundpd512): Rename to ... + (avx512f_round512): ... this. Change iterator. + (avx512f_roundps512_sfix): New define_expand. + (round2_sfix): Change iterator. + +2016-06-07 Peter Bergner + + Backport from mainline + 2016-06-07 Peter Bergner + + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mhtm and + -mno-htm. + +2016-06-07 Uros Bizjak + + PR target/71389 + * config/i386/i386.c (ix86_avx256_split_vector_move_misalign): + Copy op1 RTX to avoid invalid sharing. + (ix86_expand_vector_move_misalign): Ditto. + +2016-06-06 Jakub Jelinek + + PR tree-optimization/71259 + * tree-vect-slp.c (vect_get_constant_vectors): For + VECTOR_BOOLEAN_TYPE_P, return all ones constant instead of + one for constant op, and use COND_EXPR for non-constant. + +2016-06-06 Kyrylo Tkachov + + Backport from trunk + 2016-06-02 Kyrylo Tkachov + + PR target/70830 + * config/arm/arm.c (arm_output_multireg_pop): Guard "pop" on update. + +2016-06-05 Uros Bizjak + + Backport from mainline + 2016-06-01 Uros Bizjak + Jocelyn Mayer + + PR target/67310 + * config/i386/driver-i386.c (host_detect_local_cpu): Correctly + detect processor family for signature_CENTAUR_ebx. + : Pass c3, winchip2 or winchip-c6 for + signature_CENTAUR_ebx. + : Pass c3-2 for signature_CENTAUR_ebx. + : Pass x86-64 for has_longmode. + +2016-06-03 Jakub Jelinek + + PR middle-end/71387 + * cgraph.c (cgraph_edge::redirect_call_stmt_to_callee): If redirecting + to noreturn e->callee->decl that has void return type and void + arguments, adjust gimple_call_fntype and remove lhs even if it had + previously addressable type. + +2016-06-02 Michael Meissner + + Back port from trunk + 2016-05-26 Michael Meissner + + * config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): New function + for ISA 3.0 min/max support. + (rs6000_emit_p9_fp_cmove): New function for ISA 3.0 floating point + conditional move support. + (rs6000_emit_cmove): Call rs6000_emit_p9_fp_minmax and + rs6000_emit_p9_fp_cmove if the ISA 3.0 instructions are + available. + * config/rs6000/rs6000.md (SFDF2): New iterator to allow doing + conditional moves where the comparison type is different from move + type. + (fp_minmax): New code iterator for smin/smax. + (minmax): New code attributes for min/max. + (SMINMAX): Likewise. + (smax3): Combine min, max insns into one insn using the + fp_minmax code iterator. Add support for ISA 3.0 min/max + instructions that don't need -ffast-math. + (s3): Likewise. + (smax3_vsx): Likewise. + (smin3): Likewise. + (s3_vsx): Likewise. + (smin3_vsx): Likewise. + (pre-VSX min/max splitters): Likewise. + (s3_fpr): Likewise. + (movsfcc): Rewrite floating point conditional moves to combine + SFmode/DFmode into a single insn. + (movcc): Likewise. + (movdfcc): Likewise. + (fselsfsf4): Combine FSEL cases into a single insn, using SFDF and + SFDF2 iterators to handle all combinations. + (fseldfsf4): Likewise. + (fsel4): Likewise. + (fseldfdf4): Likewise. + (fselsfdf4): Likewise. + (movcc_p9): Add support for the ISA 3.0 + comparison instructions that set a 0/-1 mask, and use it for + floating point conditional move via XXSEL. + (fpmask): Likewise. + (xxsel): Likewise. + * config/rs6000/predicates.md (min_max_operator): Delete, no + longer used. + (fpmask_comparison_operaton): New insn for ISA 3.0 comparison + instructions that generate a 0/-1 mask for use with XXSEL. + * config/rs6000/rs6000.h (TARGET_MINMAX_SF): New helper macros to + say whether floating point min/max is available, either through + FSEL, ISA 2.06 min/max, and ISA 3.0 min/max instrucitons. + (TARGET_MINMAX_DF): Likewise. + + Back port from trunk + 2016-05-18 Michael Meissner + + * config/rs6000/predicate.md (all_ones_constant): New predicate + for vector constant with all 1's set. + +2016-06-02 Kelvin Nilsen + + Back port from trunk + 2016-05-19 Kelvin Nilsen + + * config/rs6000/altivec.md (UNSPEC_DARN): New unspec constant. + (UNSPEC_DARN_32): New unspec constant. + (UNSPEC_DARN_RAW): New unspec constant. + (darn_32): New instruction. + (darn_raw): New instruction. + (darn): New instruction. + * config/rs6000/rs6000-builtin.def (RS6000_BUILTIN_0): Add + support and documentation for this macro. + (BU_P9_MISC_1): New macro definition. + (BU_P9_64BIT_MISC_0): New macro definition. + (BU_P9_MISC_0): New macro definition. + (darn_32): New builtin definition. + (darn_raw): New builtin definition. + (darn): New builtin definition. + * config/rs6000/rs6000.c: Add #define RS6000_BUILTIN_0 and #undef + RS6000_BUILTIN_0 directives to surround each occurrence of + #include "rs6000-builtin.def". + (rs6000_builtin_mask_calculate): Add in the RS6000_BTM_MODULO and + RS6000_BTM_64BIT flags to the returned mask, depending on + configuration. + (def_builtin): Correct an error in the assignments made to the + debugging variable attr_string. + (rs6000_expand_builtin): Add support for no-operand built-in + functions. + (builtin_function_type): Remove fatal_error assertion that is no + longer valid. + (rs6000_common_init_builtins): Add support for no-operand built-in + functions. + * config/rs6000/rs6000.h (RS6000_BTM_MODULO): New macro + definition. + (RS6000_BTM_PURE): Enhance comment to clarify intent of this flag + definition. + (RS6000_BTM_64BIT): New macro definition. + * doc/extend.texi: Document __builtin_darn (void), + __builtin_darn_raw (void), and __builtin_darn_32 (void) built-in + functions. + +2016-06-01 Michael Meissner + + Back port from trunk + 2016-05-23 Michael Meissner + + PR target/71201 + * config/rs6000/altivec.md (altivec_vperm__internal): Drop + ISA 3.0 xxperm fusion alternative. + (altivec_vperm_v8hiv16qi): Likewise. + (altivec_vperm__uns_internal): Likewise. + (vperm_v8hiv4si): Likewise. + (vperm_v16qiv8hi): Likewise. + + Back port from trunk + 2016-05-23 Michael Meissner + Kelvin Nilsen + + * config/rs6000/rs6000.c (rs6000_expand_vector_set): Generate + vpermr/xxpermr on ISA 3.0. + (altivec_expand_vec_perm_le): Likewise. + * config/rs6000/altivec.md (UNSPEC_VPERMR): New unspec. + (altivec_vpermr__internal): Add VPERMR/XXPERMR support for + ISA 3.0. + + Back port from trunk + 2016-05-24 Michael Meissner + + * config/rs6000/altivec.md (VParity): New mode iterator for vector + parity built-in functions. + (p9v_ctz2): Add support for ISA 3.0 vector count trailing + zeros. + (p9v_parity2): Likewise. + * config/rs6000/vector.md (VEC_IP): New mode iterator for vector + parity. + (ctz2): ISA 3.0 expander for vector count trailing zeros. + (parity2): ISA 3.0 expander for vector parity. + * config/rs6000/rs6000-builtin.def (BU_P9_MISC_1): New macros for + power9 built-ins. + (BU_P9_64BIT_MISC_0): Likewise. + (BU_P9_MISC_0): Likewise. + (BU_P9V_AV_1): Likewise. + (BU_P9V_AV_2): Likewise. + (BU_P9V_AV_3): Likewise. + (BU_P9V_AV_P): Likewise. + (BU_P9V_VSX_1): Likewise. + (BU_P9V_OVERLOAD_1): Likewise. + (BU_P9V_OVERLOAD_2): Likewise. + (BU_P9V_OVERLOAD_3): Likewise. + (VCTZB): Add vector count trailing zeros support. + (VCTZH): Likewise. + (VCTZW): Likewise. + (VCTZD): Likewise. + (VPRTYBD): Add vector parity support. + (VPRTYBQ): Likewise. + (VPRTYBW): Likewise. + (VCTZ): Add overloaded vector count trailing zeros support. + (VPRTYB): Add overloaded vector parity support. + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + overloaded vector count trailing zeros and parity instructions. + * config/rs6000/rs6000.md (wd mode attribute): Add V1TI and TI for + vector parity support. + * config/rs6000/altivec.h (vec_vctz): Add ISA 3.0 vector count + trailing zeros support. + (vec_cntlz): Likewise. + (vec_vctzb): Likewise. + (vec_vctzd): Likewise. + (vec_vctzh): Likewise. + (vec_vctzw): Likewise. + (vec_vprtyb): Add ISA 3.0 vector parity support. + (vec_vprtybd): Likewise. + (vec_vprtybw): Likewise. + (vec_vprtybq): Likewise. + * doc/extend.texi (PowerPC AltiVec Built-in Functions): Document + the ISA 3.0 vector count trailing zeros and vector parity built-in + functions. + + Back port from trunk + 2016-05-24 Michael Meissner + + * config/rs6000/altivec.md (VNEG iterator): New iterator for + VNEGW/VNEGD instructions. + (p9_neg2): New insns for ISA 3.0 VNEGW/VNEGD. + (neg2): Add expander for V2DImode added in ISA 2.07, and + support for ISA 3.0 VNEGW/VNEGD instructions. + + Back port from trunk + 2016-05-11 Michael Meissner + + * config/rs6000/predicates.md (quad_memory_operand): Move most of + the code into quad_address_p and call it to share code with + vsx_quad_dform_memory_operand. + (vsx_quad_dform_memory_operand): New predicate for ISA 3.0 vector + d-form support. + * config/rs6000/rs6000.opt (-mlra): Switch to being an option mask + bit instead of being a separate word. Split -mpower9-dform into + two switches, -mpower9-dform-scalar and -mpower9-dform-vector. + * config/rs6000/rs6000.c (RELOAD_REG_QUAD_OFFSET): New addr_mask + for the register class supporting 128-bit quad word memory offsets. + (mode_supports_vsx_dform_quad): Helper function to return if the + register class uses quad word memory offsets. + (rs6000_debug_addr_mask): Add support for quad word memory offsets. + (rs6000_debug_reg_global): Always print if we are using LRA or not. + (rs6000_setup_reg_addr_masks): If ISA 3.0 vector d-form + instructions are enabled, set up the appropriate addr_masks for + 128-bit types. + (rs6000_init_hard_regno_mode_ok): wb constraint is now based on + -mpower9-dform-scalar, instead of -mpower9-dform. + (rs6000_option_override_internal): Split -mpower9-dform into two + switches, -mpower9-dform-scalar and -mpower9-dform-vector. The + -mpower9-dform switch sets or clears both. If we are not using + the LRA register allocator, do not enable -mpower9-dform-vector by + default. If we are using LRA, enable -mpower9-dform-vector and + -mvsx-timode if it is appropriate. Issue a warning if either + -mpower9-dform-vector or -mvsx-timode are explicitly used without + enabling LRA. + (quad_address_offset_p): New helper function to return if the + offset is legal for quad word memory instructions. + (quad_address_p): New function to determin if GPR or vector + register quad word memory addresses are legal. + (mem_operand_gpr): Validate quad word address offsets. + (reg_offset_addressing_ok_p): Add support for ISA 3.0 vector + d-form (register + offset) instructions. + (offsettable_ok_by_alignment): Likewise. + (rs6000_legitimate_offset_address_p): Likewise. + (legitimate_lo_sum_address_p): Likewise. + (rs6000_legitimize_address): Likewise. + (rs6000_legitimize_reload_address): Add more debug statements for + -mdebug=addr. + (rs6000_legitimate_address_p): Add support for ISA 3.0 vector + d-form instructions. + (rs6000_secondary_reload_memory): Add support for ISA 3.0 vector + d-form instructions. Distinguish different cases in debug + output. (rs6000_secondary_reload_inner): Add support for ISA 3.0 vector + d-form instructions. + (rs6000_preferred_reload_class): Likewise. + (rs6000_output_move_128bit): Add support for ISA 3.0 d-form + instructions. If ISA 3.0 is available, generate lxvx/stxvx instead + of the ISA 2.06 indexed memory instructions. + (rs6000_emit_prologue): If we have ISA 3.0 d-form instructions, + use them to save/restore the saved vector registers instead of + using Altivec instructions. + (rs6000_emit_epilogue): Likewise. + (rs6000_lra_p): Use TARGET_LRA instead of the old option word. + (rs6000_opt_masks): Split -mpower9-dform into + -mpower9-dform-scalar and -mpower9-dform-vector. + (rs6000_print_options_internal): Print -mno- if + was not selected. + * config/rs6000/vsx.md (p9_vecload_): Delete hack to emit + ISA 3.0 vector indexed memory instructions, and fold the code into + the normal mov patterns. + (p9_vecstore_): Likewise. + (vsx_mov): Add support for ISA 3.0 vector d-form + instructions. + (vsx_movti_64bit): Likewise. + (vsx_movti_32bit): Likewise. + * config/rs6000/constraints.md (wO constraint): New constraint for + ISA 3.0 vector d-form support. + * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Use + -mpower9-dform-scalar instead of -mpower9-dform. Add note not to + include -mpower9-dform-vector until we switch over to LRA. + (POWERPC_MASKS): Add -mlra. Split -mpower9-dform into two. + switches, -mpower9-dform-scalar and -mpower9-dform-vector. + * config/rs6000/rs6000-protos.h (quad_address_p): Add declaration. + * doc/invoke.texi (RS/6000 and PowerPC Options): Add documentation + for -mpower9-dform and -mlra. + * doc/md.texi (wO constraint): Document wO constraint. + +2016-06-01 Eric Botcazou + + * tree-vect-loop.c (vect_determine_vectorization_factor): Also compute + the factor for live Phi nodes. + +2016-06-01 Jakub Jelinek + + PR middle-end/71371 + * gimplify.c (gimplify_omp_for): Temporarily clear gimplify_omp_ctxp + around creation of the temporary. + +2016-06-01 Eric Botcazou + + * tree-vect-loop.c (vect_determine_vectorization_factor): Also take + into account live statements for mask producers. + +2016-05-31 Richard Biener + + Backport from mainline + 2016-05-11 Richard Biener + + PR debug/71057 + * dwarf2out.c (retry_incomplete_types): Set early_dwarf. + (dwarf2out_finish): Move retry_incomplete_types call ... + (dwarf2out_early_finish): ... here. + +2016-05-31 Kyrylo Tkachov + + PR target/71056 + * config/arm/arm-builtins.c (arm_builtin_vectorized_function): Return + NULL_TREE early if NEON is not available. Remove now redundant check + in ARM_CHECK_BUILTIN_MODE. + +2016-05-31 Tom de Vries + + backport: + 2016-05-31 Tom de Vries + + PR tree-optimization/69068 + * graphite-isl-ast-to-gimple.c (copy_bb_and_scalar_dependences): Handle + phis with more than two args. + +2016-05-30 Andreas Tobler + + Backport from mainline + 2016-05-30 Andreas Tobler + + * config.gcc: Move hard float support for arm*hf*-*-freebsd* into + armv6*-*-freebsd* for FreeBSD 11. Eliminate the arm*hf*-*-freebsd* + target. + +2016-05-30 Bill Schmidt + + Backport from mainline + 2016-04-29 Bill Schmidt + + * config/rs6000/altivec.h: Change definitions of vec_xl and + vec_xst. + * config/rs6000/rs6000-builtin.def (LD_ELEMREV_V2DF): New. + (LD_ELEMREV_V2DI): New. + (LD_ELEMREV_V4SF): New. + (LD_ELEMREV_V4SI): New. + (LD_ELEMREV_V8HI): New. + (LD_ELEMREV_V16QI): New. + (ST_ELEMREV_V2DF): New. + (ST_ELEMREV_V2DI): New. + (ST_ELEMREV_V4SF): New. + (ST_ELEMREV_V4SI): New. + (ST_ELEMREV_V8HI): New. + (ST_ELEMREV_V16QI): New. + (XL): New. + (XST): New. + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + descriptions for VSX_BUILTIN_VEC_XL and VSX_BUILTIN_VEC_XST. + * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Map from + TARGET_P9_VECTOR to RS6000_BTM_P9_VECTOR. + (altivec_expand_builtin): Add handling for + VSX_BUILTIN_ST_ELEMREV_ and VSX_BUILTIN_LD_ELEMREV_. + (rs6000_invalid_builtin): Add error-checking for + RS6000_BTM_P9_VECTOR. + (altivec_init_builtins): Define builtins used to implement vec_xl + and vec_xst. + (rs6000_builtin_mask_names): Define power9-vector. + * config/rs6000/rs6000.h (MASK_P9_VECTOR): Define. + (RS6000_BTM_P9_VECTOR): Define. + (RS6000_BTM_COMMON): Include RS6000_BTM_P9_VECTOR. + * config/rs6000/vsx.md (vsx_ld_elemrev_v2di): New define_insn. + (vsx_ld_elemrev_v2df): Likewise. + (vsx_ld_elemrev_v4sf): Likewise. + (vsx_ld_elemrev_v4si): Likewise. + (vsx_ld_elemrev_v8hi): Likewise. + (vsx_ld_elemrev_v16qi): Likewise. + (vsx_st_elemrev_v2df): Likewise. + (vsx_st_elemrev_v2di): Likewise. + (vsx_st_elemrev_v4sf): Likewise. + (vsx_st_elemrev_v4si): Likewise. + (vsx_st_elemrev_v8hi): Likewise. + (vsx_st_elemrev_v16qi): Likewise. + * doc/extend.texi: Add prototypes for vec_xl and vec_xst. Correct + grammar. + +2016-05-30 Richard Biener + + Backport from mainline + 2016-05-11 Richard Biener + + PR middle-end/71002 + * alias.c (reference_alias_ptr_type): Preserve alias-set zero + if the langhook insists on it. + * fold-const.c (make_bit_field_ref): Add arg for the original + reference and preserve its alias-set. + (decode_field_reference): Take exp by reference and adjust it + to the original memory reference. + (optimize_bit_field_compare): Adjust callers. + (fold_truth_andor_1): Likewise. + + 2016-05-13 Jakub Jelinek + + PR bootstrap/71071 + * fold-const.c (fold_checksum_tree): Allow modification + of TYPE_ALIAS_SET during folding. + +2016-05-30 Eric Botcazou + + * config/visium/visium.c (visium_split_double_add): Minor tweaks. + (visium_expand_copysign): Use gen_int_mode directly. + (visium_compute_frame_size): Minor tweaks. + +2016-05-30 Tom de Vries + + backport: + 2016-05-30 Tom de Vries + + PR tree-optimization/69067 + * graphite-isl-ast-to-gimple.c (get_def_bb_for_const): Remove assert. + +2016-05-27 Eric Botcazou + + * config/visium/visium-protos.h (split_double_move): Rename into... + (visium_split_double_move): ...this. + (visium_split_double_add): Declare. + * config/visium/visium.c (split_double_move): Rename into... + (visium_split_double_move): ...this. + (visium_split_double_add): New function. + (visium_expand_copysign): Renumber operands for consistency. + * config/visium/visium.md (DImode move splitter): Adjust to renaming. + (DFmode move splitter): Likewise. + (*addi3_insn): Split by means of visium_split_double_add. + (*adddi3_insn_flags): Delete. + (*plus_plus_sltu): New insn. + (*subdi3_insn): Split by means of visium_split_double_add. + (subdi3_insn_flags): Delete. + (*minus_minus_sltu): New insn. + (*negdi2_insn): Split by means of visium_split_double_add. + (*negdi2_insn_flags): Delete. + +2016-05-27 Ilya Enkovich + + Backport from mainline r236810. + 2016-05-27 Ilya Enkovich + + PR middle-end/71279 + * fold-const.c (fold_ternary_loc): Don't fold VEC_COND_EXPR + into comparison. + +2016-05-25 Eric Botcazou + + * tree-ssa-phiopt.c (factor_out_conditional_conversion): Remove + redundant test and bail out if the type of the new operand is not + a GIMPLE register type after stripping a VIEW_CONVERT_EXPR. + +2016-05-24 Martin Sebor + + PR c++/71147 + * tree.h (complete_or_array_type_p): New inline function. + +2016-05-24 Jakub Jelinek + + * config/i386/i386.h (TARGET_AVOID_4BYTE_PREFIXES): Define. + * config/i386/constraints.md (Yr): Test TARGET_AVOID_4BYTE_PREFIXES + rather than X86_TUNE_AVOID_4BYTE_PREFIXES. Use SSE_REGS instead + of ALL_SSE_REGS. Return SSE_REGS also when TARGET_AVX. + +2016-05-24 Jakub Jelinek + + PR c++/71257 + * tree-vect-stmts.c (vectorizable_simd_clone_call): Handle + SIMD_CLONE_ARG_TYPE_LINEAR_REF_CONSTANT_STEP like + SIMD_CLONE_ARG_TYPE_LINEAR_CONSTANT_STEP. Add + SIMD_CLONE_ARG_TYPE_LINEAR_VAL_CONSTANT_STEP and + SIMD_CLONE_ARG_TYPE_LINEAR_UVAL_CONSTANT_STEP cases explicitly. + +2016-05-23 Martin Jambor + + * hsa-gen.c (gen_hsa_insns_for_switch_stmt): Create an empty + default block if a PHI node in the original one would be resized. + +2016-05-23 Martin Jambor + + PR tree-optimization/70884 + * tree-sra.c (initialize_constant_pool_replacements): Do not check + should_scalarize_away_bitmap and cannot_scalarize_away_bitmap bits. + (sort_and_splice_var_accesses): Do not consider multiple scalar reads + of constant pool data as a reason for scalarization. + +2016-05-20 Eric Botcazou + + * config/arm/arm.c (arm_expand_prologue): Set the stack usage to 0 + for naked functions. + (thumb1_expand_prologue): Likewise. + +2016-05-20 Jakub Jelinek + + PR c++/71210 + * gimple-fold.c (gimple_fold_call): Do not remove lhs of noreturn + calls if the LHS is variable length or has addressable type. + If targets[0]->decl is a noreturn call with void return type and + zero arguments, adjust fntype and remove lhs in that case. + +2016-05-20 Uros Bizjak + + * sched-deps.c (sched_analyze_2) : Also + force pending loads from memory. + +2016-05-19 Marek Polacek + + Backport from mainline + 2016-05-19 Marek Polacek + + PR tree-optimization/71031 + * tree-vrp.c (extract_range_from_binary_expr_1): Turn assert into a + condition and adjust the code a bit. + +2016-05-19 Martin Jambor + + PR ipa/70646 + * ipa-prop.c (determine_locally_known_aggregate_parts): Bail out early + if parameter PARAM_IPA_MAX_AGG_ITEMS is zero. + +2016-05-19 Martin Jambor + + PR ipa/70646 + * ipa-inline.h (condition): New field size. + * ipa-inline-analysis.c (add_condition): New parameter SIZE, use it + for comaprison and store it into the new condition. + (evaluate_conditions_for_known_args): Use condition size to check + access sizes for all but CHANGED conditions. + (unmodified_parm_1): New parameter size_p, store access size into it. + (unmodified_parm): Likewise. + (unmodified_parm_or_parm_agg_item): Likewise. + (eliminated_by_inlining_prob): Pass NULL to unmodified_parm as size_p. + (set_cond_stmt_execution_predicate): Extract access sizes and store + them to conditions. + (set_switch_stmt_execution_predicate): Likewise. + (will_be_nonconstant_expr_predicate): Likewise. + (will_be_nonconstant_predicate): Likewise. + (inline_read_section): Stream condition size. + (inline_write_summary): Likewise. + * lto-streamer.h (LTO_minor_version): Bump. + +2016-05-18 Martin Liska + + Backport from mainline + 2016-05-18 Martin Liska + + PR fortran/70856 + * ipa-icf.c (sem_variable::merge): Set DECL_PT_UID for + merged variables. + +2016-05-18 Jakub Jelinek + + PR c++/71100 + * cgraph.c (cgraph_edge::redirect_call_stmt_to_callee): Don't drop + lhs if it has TREE_ADDRESSABLE type. + +2016-05-18 Uros Bizjak + + PR target/71145 + * config/alpha/alpha.md (trap): Add (use (reg:DI 29)). + (*exception_receiver_1): Return "#" for TARGET_EXPLICIT_RELOCS. + +2016-05-17 Thomas Schwinge + + Backport trunk r235748: + PR target/70860 + * config/nvptx/nvptx.c (nvptx_libcall_value): Handle NULL cfun. + (nvptx_function_value): Assert non-NULL cfun. + +2016-05-17 Kyrylo Tkachov + + Backport from mainline + 2016-05-17 Kyrylo Tkachov + + PR target/70809 + * config/aarch64/aarch64-simd.md (aarch64_vmls): Delete. + +2016-05-16 Martin Jambor + + * hsa-gen.c (fillup_for_decl): Increase alignment to natural one. + (get_symbol_for_decl): Sorry if a global symbol in under-aligned. + +2016-05-16 Martin Jambor + + PR hsa/70857 + * omp-low.c (grid_expand_target_grid_body): Copy RESULT_DECL of + the outlined kernel function. + +2016-05-16 James Norris + + Backport from mainline r236098. + 2016-05-10 James Norris + + PR driver/68463 + * config/rs6000/sysv4.h (CRTOFFLOADBEGIN): Define. Add crtoffloadbegin.o + if offloading is enabled and -fopenacc or -fopenmp is specified. + (CRTOFFLOADEND): Likewise. + (STARTFILE_LINUX_SPEC): Add CRTOFFLOADBEGIN. + (ENDFILE_LINUX_SPEC): Add CRTOFFLOADEND. + +2016-05-16 Alan Modra + + Apply from mainline + 2016-05-10 Alan Modra + PR target/70947 + * config/rs6000/rs6000.c (rs6000_expand_split_stack_prologue): Stop + regrename modifying insns saving lr before __morestack call. + * config/rs6000/rs6000.md (split_stack_return): Similarly for + insns restoring lr after __morestack call. + +2016-05-13 Richard Biener + + Backport from mainline + 2016-04-27 Richard Biener + + PR ipa/70760 + * tree-ssa-structalias.c (find_func_aliases_for_call): Use + aggregate_value_p to determine if a function result is + returned by reference. + + 2016-05-06 Richard Biener + + PR middle-end/70931 + * dwarf2out.c (native_encode_initializer): Skip zero-sized fields. + + 2016-05-06 Richard Biener + + PR middle-end/70941 + * fold-const.c (split_tree): Always convert to the original type + before negating. + +2016-05-12 Martin Liska + + Backport from mainline + 2016-05-10 Martin Liska + + * tree-inline.c (remap_dependence_clique): Do not remap + debugging statements. + +2016-05-12 Ilya Enkovich + + Backport from mainline r236171. + 2016-05-12 Ilya Enkovich + + PR tree-optimization/71006 + * tree-vect-loop.c (vect_determine_vectorization_factor): Don't + consider COND_EXPR as a mask producer. + +2016-05-12 Kyrylo Tkachov + + Backport from mainline + 2016-05-12 Kyrylo Tkachov + + PR target/70830 + * config/arm/arm.c (arm_output_multireg_pop): Avoid POP instruction + when popping the PC and within an interrupt handler routine. + Add missing tab to output of "ldmfd". + (output_return_instruction): Output LDMFD with SP update rather + than POP when returning from interrupt handler. + +2016-05-11 Ilya Enkovich + + Backport from mainline r236088. + 2016-05-10 Ilya Enkovich + + PR middle-end/70877 + * tree-chkp.c (chkp_add_bounds_to_call_stmt): Handle + calls with type casted fndecl. + +2016-05-11 Ilya Enkovich + + Backport from mainline r236086. + 2016-05-10 Ilya Enkovich + + PR tree-optimization/70876 + * tree-chkp.c (chkp_find_bounds_1): Support WITH_SIZE_EXPR. + * gcc/calls.c (initialize_argument_information): Bind bounds + with corresponding args passed by reference. + +2016-05-10 Bill Schmidt + + Backport from mainline + 2016-05-10 Bill Schmidt + + PR target/70963 + * config/rs6000/vsx.md (vsx_xvcvdpsxds_scale): Generate correct + code for a zero scale factor. + (vsx_xvcvdpuxds_scale): Likewise. + +2016-05-10 Jakub Jelinek + + Backported from mainline + 2016-05-03 Jakub Jelinek + + PR tree-optimization/70916 + * tree-vect-patterns.c (vect_recog_mask_conversion_pattern): Give up + if COND_EXPR rhs1 is neither SSA_NAME nor COMPARISON_CLASS_P. + +2016-05-10 Yuri Rumyantsev + + Backport from mainline r235962. + 2016-05-06 Yuri Rumyantsev + + PR debug/70935 + * tree-ssa-loop-unswitch.c (find_loop_guard): Reject guard edge with + loop latch destination. + +2016-05-10 Andreas Krebbel + + Backport from mainline + 2016-05-10 Andreas Krebbel + + * config/s390/s390.md ("*vec_cmpdf_cconly") + ("*fixuns_truncdfdi2_z13") + ("*fixuns_trunc2_z196") + ("*fix_truncdfdi2_bfp_z13", "*floatunsdidf2_z13") + ("*extendsfdf2_z13"): Replace TARGET_Z13 with TARGET_VX. + +2016-05-10 Sebastian Huber + + Backport from mainline + 2016-04-27 Sebastian Huber + + * config/rtems.h (LIB_SPEC): Add -latomic. + +2016-05-10 Sebastian Huber + + Backport from mainline + 2016-04-27 Joel Sherrill + + * config/microblaze/rtems.h: Redefine LINK_SPEC to avoid + xilink.ld and flags not relevant to RTEMS. + +2016-05-09 Uros Bizjak + + * config/i386/i386.md (absneg splitters with general regs): Use + general_reg_operand predicate. + (btsq peephole2): Use x86_64_immediate_operand to check if new + value is suitable for immediate operand. Generate emitted insn + using RTL expressions. + (btcq peephole2): Ditto. + (btrq peephole2): Ditto. Generate correct immediate operand + for AND masking. + 2016-05-07 Tom de Vries backport: @@ -158,7 +1219,7 @@ constant boolean. 2016-04-20 Andrew Pinski - Kyrylo Tkachov + Kyrylo Tkachov PR target/64971 * config/aarch64/aarch64.md (sibcall): Force call diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 7aaf7de..8cee680 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20160509 +20160615 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 9856530..233e097 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,50 @@ +2016-06-13 Eric Botcazou + + * gcc-interface/decl.c (gnat_to_gnu_entity) : Deal with + PLUS_EXPR in the expression of a renaming. + +2016-06-11 Eric Botcazou + + * gcc-interface/trans.c (Case_Statement_to_gnu): Deal with characters. + +2016-06-11 Pierre-Marie de Rodat + + * gcc-interface/decl.c (gnat_to_gnu_entity): Do not clobber + gnat_entity_name with temporary names for XUP and XUT types. + +2016-06-06 Eric Botcazou + + * gcc-interface/utils.c (gnat_internal_attribute_table): Add support + for noinline and noclone attributes. + (handle_noinline_attribute): New handler. + (handle_noclone_attribute): Likewise. + +2016-06-06 Eric Botcazou + + * gcc-interface/utils2.c (build_call_alloc_dealloc): Do not substitute + placeholder expressions here but... + * gcc-interface/trans.c (gnat_to_gnu) : ...here. + Make an exception to the protection of a CALL_EXPR result with an + unconstrained type only in the same cases as Call_to_gnu. + +2016-06-01 Simon Wright + + PR ada/71358 + * g-comlin.adb (Display_Section_Help): Do not dereference + Config.Switches if it's null. + (Getopt): Likewise. + +2016-05-31 Eric Botcazou + + * s-osinte-kfreebsd-gnu.ads (clock_getres): Define. + (Get_Page_Size): Remove duplicate and return int. + +2016-05-31 Jan Sommer + + PR ada/71317 + * s-osinte-rtems.ads (clock_getres): Define. + (Get_Page_Size): Remove duplicate and return int. + 2016-05-06 Eric Botcazou PR ada/70969 diff --git a/gcc/ada/g-comlin.adb b/gcc/ada/g-comlin.adb index de2f3f9..172edaf 100644 --- a/gcc/ada/g-comlin.adb +++ b/gcc/ada/g-comlin.adb @@ -6,7 +6,7 @@ -- -- -- B o d y -- -- -- --- Copyright (C) 1999-2015, Free Software Foundation, Inc. -- +-- Copyright (C) 1999-2016, Free Software Foundation, Inc. -- -- -- -- GNAT is free software; you can redistribute it and/or modify it under -- -- terms of the GNU General Public License as published by the Free Soft- -- @@ -3151,16 +3151,18 @@ package body GNAT.Command_Line is New_Line; - if Section /= "" then + if Section /= "" and then Config.Switches /= null then Put_Line ("Switches after " & Section); end if; -- Compute size of the switches column - for S in Config.Switches'Range loop - Max_Len := Natural'Max - (Max_Len, Switch_Name (Config.Switches (S), Section)'Length); - end loop; + if Config.Switches /= null then + for S in Config.Switches'Range loop + Max_Len := Natural'Max + (Max_Len, Switch_Name (Config.Switches (S), Section)'Length); + end loop; + end if; if Config.Aliases /= null then for A in Config.Aliases'Range loop @@ -3173,25 +3175,27 @@ package body GNAT.Command_Line is -- Display the switches - for S in Config.Switches'Range loop - declare - N : constant String := - Switch_Name (Config.Switches (S), Section); + if Config.Switches /= null then + for S in Config.Switches'Range loop + declare + N : constant String := + Switch_Name (Config.Switches (S), Section); - begin - if N /= "" then - Put (" "); - Put (N); - Put ((1 .. Max_Len - N'Length + 1 => ' ')); + begin + if N /= "" then + Put (" "); + Put (N); + Put ((1 .. Max_Len - N'Length + 1 => ' ')); - if Config.Switches (S).Help /= null then - Put (Config.Switches (S).Help.all); - end if; + if Config.Switches (S).Help /= null then + Put (Config.Switches (S).Help.all); + end if; - New_Line; - end if; - end; - end loop; + New_Line; + end if; + end; + end loop; + end if; -- Display the aliases @@ -3454,25 +3458,27 @@ package body GNAT.Command_Line is -- Initialize output values for automatically handled switches - for S in Config.Switches'Range loop - case Config.Switches (S).Typ is - when Switch_Untyped => - null; -- Nothing to do + if Config.Switches /= null then + for S in Config.Switches'Range loop + case Config.Switches (S).Typ is + when Switch_Untyped => + null; -- Nothing to do - when Switch_Boolean => - Config.Switches (S).Boolean_Output.all := - not Config.Switches (S).Boolean_Value; + when Switch_Boolean => + Config.Switches (S).Boolean_Output.all := + not Config.Switches (S).Boolean_Value; - when Switch_Integer => - Config.Switches (S).Integer_Output.all := - Config.Switches (S).Integer_Initial; + when Switch_Integer => + Config.Switches (S).Integer_Output.all := + Config.Switches (S).Integer_Initial; - when Switch_String => - if Config.Switches (S).String_Output.all = null then - Config.Switches (S).String_Output.all := new String'(""); - end if; - end case; - end loop; + when Switch_String => + if Config.Switches (S).String_Output.all = null then + Config.Switches (S).String_Output.all := new String'(""); + end if; + end case; + end loop; + end if; -- For all sections, and all switches within those sections diff --git a/gcc/ada/gcc-interface/decl.c b/gcc/ada/gcc-interface/decl.c index 87026e7..6f2b0bb 100644 --- a/gcc/ada/gcc-interface/decl.c +++ b/gcc/ada/gcc-interface/decl.c @@ -966,6 +966,7 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, int definition) && !call_is_atomic_load (inner)) || TREE_CODE (inner) == ADDR_EXPR || TREE_CODE (inner) == NULL_EXPR + || TREE_CODE (inner) == PLUS_EXPR || TREE_CODE (inner) == CONSTRUCTOR || CONSTANT_CLASS_P (inner) /* We need to detect the case where a temporary is created to @@ -2321,10 +2322,12 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, int definition) gnat_name = Packed_Array_Impl_Type (gnat_entity); else gnat_name = gnat_entity; - if (gnat_encodings != DWARF_GNAT_ENCODINGS_MINIMAL) - gnu_entity_name = create_concat_name (gnat_name, "XUP"); - create_type_decl (gnu_entity_name, gnu_fat_type, artificial_p, - debug_info_p, gnat_entity); + tree xup_name + = (gnat_encodings == DWARF_GNAT_ENCODINGS_MINIMAL) + ? get_entity_name (gnat_name) + : create_concat_name (gnat_name, "XUP"); + create_type_decl (xup_name, gnu_fat_type, artificial_p, debug_info_p, + gnat_entity); /* Create the type to be designated by thin pointers: a record type for the array and its template. We used to shift the fields to have the @@ -2334,11 +2337,11 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, int definition) Note that GDB can handle standard DWARF information for them, so we don't have to name them as a GNAT encoding, except if specifically asked to. */ - if (gnat_encodings != DWARF_GNAT_ENCODINGS_MINIMAL) - gnu_entity_name = create_concat_name (gnat_name, "XUT"); - else - gnu_entity_name = get_entity_name (gnat_name); - tem = build_unc_object_type (gnu_template_type, tem, gnu_entity_name, + tree xut_name + = (gnat_encodings == DWARF_GNAT_ENCODINGS_MINIMAL) + ? get_entity_name (gnat_name) + : create_concat_name (gnat_name, "XUT"); + tem = build_unc_object_type (gnu_template_type, tem, xut_name, debug_info_p); SET_TYPE_UNCONSTRAINED_ARRAY (tem, gnu_type); diff --git a/gcc/ada/gcc-interface/trans.c b/gcc/ada/gcc-interface/trans.c index 357d26f..cf64d22 100644 --- a/gcc/ada/gcc-interface/trans.c +++ b/gcc/ada/gcc-interface/trans.c @@ -2483,13 +2483,15 @@ Attribute_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p, int attribute) static tree Case_Statement_to_gnu (Node_Id gnat_node) { - tree gnu_result, gnu_expr, gnu_label; + tree gnu_result, gnu_expr, gnu_type, gnu_label; Node_Id gnat_when; location_t end_locus; bool may_fallthru = false; gnu_expr = gnat_to_gnu (Expression (gnat_node)); gnu_expr = convert (get_base_type (TREE_TYPE (gnu_expr)), gnu_expr); + gnu_expr = maybe_character_value (gnu_expr); + gnu_type = TREE_TYPE (gnu_expr); /* We build a SWITCH_EXPR that contains the code with interspersed CASE_LABEL_EXPRs for each label. */ @@ -2559,6 +2561,11 @@ Case_Statement_to_gnu (Node_Id gnat_node) gcc_assert (!gnu_low || TREE_CODE (gnu_low) == INTEGER_CST); gcc_assert (!gnu_high || TREE_CODE (gnu_high) == INTEGER_CST); + if (gnu_low && TREE_TYPE (gnu_low) != gnu_type) + gnu_low = convert (gnu_type, gnu_low); + if (gnu_high && TREE_TYPE (gnu_high) != gnu_type) + gnu_high = convert (gnu_type, gnu_high); + add_stmt_with_node (build_case_label (gnu_low, gnu_high, label), gnat_choice); choices_added_p = true; @@ -2590,8 +2597,8 @@ Case_Statement_to_gnu (Node_Id gnat_node) /* Now emit a definition of the label the cases branch to, if any. */ if (may_fallthru) add_stmt (build1 (LABEL_EXPR, void_type_node, gnu_label)); - gnu_result = build3 (SWITCH_EXPR, TREE_TYPE (gnu_expr), gnu_expr, - end_stmt_group (), NULL_TREE); + gnu_result + = build3 (SWITCH_EXPR, gnu_type, gnu_expr, end_stmt_group (), NULL_TREE); return gnu_result; } @@ -7635,10 +7642,11 @@ gnat_to_gnu (Node_Id gnat_node) else gnu_actual_obj_type = gnu_obj_type; + tree gnu_size = TYPE_SIZE_UNIT (gnu_actual_obj_type); + gnu_size = SUBSTITUTE_PLACEHOLDER_IN_EXPR (gnu_size, gnu_ptr); + gnu_result - = build_call_alloc_dealloc (gnu_ptr, - TYPE_SIZE_UNIT (gnu_actual_obj_type), - gnu_obj_type, + = build_call_alloc_dealloc (gnu_ptr, gnu_size, gnu_obj_type, Procedure_To_Call (gnat_node), Storage_Pool (gnat_node), gnat_node); @@ -7719,16 +7727,22 @@ gnat_to_gnu (Node_Id gnat_node) N_Raise_Constraint_Error)); } - /* If the result has side-effects and is of an unconstrained type, make a - SAVE_EXPR so that we can be sure it will only be referenced once. But - this is useless for a call to a function that returns an unconstrained - type with default discriminant, as we cannot compute the size of the - actual returned object. We must do this before any conversions. */ + /* If the result has side-effects and is of an unconstrained type, protect + the expression in case it will be referenced multiple times, i.e. for + its value and to compute the size of an object. But do it neither for + an object nor a renaming declaration, nor a return statement of a call + to a function that returns an unconstrained record type with default + discriminant, because there is no size to be computed in these cases + and this will create a useless temporary. We must do this before any + conversions. */ if (TREE_SIDE_EFFECTS (gnu_result) - && !(TREE_CODE (gnu_result) == CALL_EXPR - && type_is_padding_self_referential (TREE_TYPE (gnu_result))) && (TREE_CODE (gnu_result_type) == UNCONSTRAINED_ARRAY_TYPE - || CONTAINS_PLACEHOLDER_P (TYPE_SIZE (gnu_result_type)))) + || CONTAINS_PLACEHOLDER_P (TYPE_SIZE (gnu_result_type))) + && !(TREE_CODE (gnu_result) == CALL_EXPR + && type_is_padding_self_referential (TREE_TYPE (gnu_result)) + && (Nkind (Parent (gnat_node)) == N_Object_Declaration + || Nkind (Parent (gnat_node)) == N_Object_Renaming_Declaration + || Nkind (Parent (gnat_node)) == N_Simple_Return_Statement))) gnu_result = gnat_protect_expr (gnu_result); /* Now convert the result to the result type, unless we are in one of the diff --git a/gcc/ada/gcc-interface/utils.c b/gcc/ada/gcc-interface/utils.c index 9bd2773..4226f95 100644 --- a/gcc/ada/gcc-interface/utils.c +++ b/gcc/ada/gcc-interface/utils.c @@ -90,6 +90,8 @@ static tree handle_novops_attribute (tree *, tree, tree, int, bool *); static tree handle_nonnull_attribute (tree *, tree, tree, int, bool *); static tree handle_sentinel_attribute (tree *, tree, tree, int, bool *); static tree handle_noreturn_attribute (tree *, tree, tree, int, bool *); +static tree handle_noinline_attribute (tree *, tree, tree, int, bool *); +static tree handle_noclone_attribute (tree *, tree, tree, int, bool *); static tree handle_leaf_attribute (tree *, tree, tree, int, bool *); static tree handle_always_inline_attribute (tree *, tree, tree, int, bool *); static tree handle_malloc_attribute (tree *, tree, tree, int, bool *); @@ -121,6 +123,10 @@ const struct attribute_spec gnat_internal_attribute_table[] = false }, { "noreturn", 0, 0, true, false, false, handle_noreturn_attribute, false }, + { "noinline", 0, 0, true, false, false, handle_noinline_attribute, + false }, + { "noclone", 0, 0, true, false, false, handle_noclone_attribute, + false }, { "leaf", 0, 0, true, false, false, handle_leaf_attribute, false }, { "always_inline",0, 0, true, false, false, handle_always_inline_attribute, @@ -5974,6 +5980,51 @@ handle_noreturn_attribute (tree *node, tree name, tree ARG_UNUSED (args), return NULL_TREE; } +/* Handle a "noinline" attribute; arguments as in + struct attribute_spec.handler. */ + +static tree +handle_noinline_attribute (tree *node, tree name, + tree ARG_UNUSED (args), + int ARG_UNUSED (flags), bool *no_add_attrs) +{ + if (TREE_CODE (*node) == FUNCTION_DECL) + { + if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (*node))) + { + warning (OPT_Wattributes, "%qE attribute ignored due to conflict " + "with attribute %qs", name, "always_inline"); + *no_add_attrs = true; + } + else + DECL_UNINLINABLE (*node) = 1; + } + else + { + warning (OPT_Wattributes, "%qE attribute ignored", name); + *no_add_attrs = true; + } + + return NULL_TREE; +} + +/* Handle a "noclone" attribute; arguments as in + struct attribute_spec.handler. */ + +static tree +handle_noclone_attribute (tree *node, tree name, + tree ARG_UNUSED (args), + int ARG_UNUSED (flags), bool *no_add_attrs) +{ + if (TREE_CODE (*node) != FUNCTION_DECL) + { + warning (OPT_Wattributes, "%qE attribute ignored", name); + *no_add_attrs = true; + } + + return NULL_TREE; +} + /* Handle a "leaf" attribute; arguments as in struct attribute_spec.handler. */ diff --git a/gcc/ada/gcc-interface/utils2.c b/gcc/ada/gcc-interface/utils2.c index c1bb74d..6f05ee2 100644 --- a/gcc/ada/gcc-interface/utils2.c +++ b/gcc/ada/gcc-interface/utils2.c @@ -2266,8 +2266,6 @@ build_call_alloc_dealloc (tree gnu_obj, tree gnu_size, tree gnu_type, Entity_Id gnat_proc, Entity_Id gnat_pool, Node_Id gnat_node) { - gnu_size = SUBSTITUTE_PLACEHOLDER_IN_EXPR (gnu_size, gnu_obj); - /* Explicit proc to call ? This one is assumed to deal with the type alignment constraints. */ if (Present (gnat_proc)) diff --git a/gcc/ada/s-osinte-kfreebsd-gnu.ads b/gcc/ada/s-osinte-kfreebsd-gnu.ads index 3f6ef9b..647778b 100644 --- a/gcc/ada/s-osinte-kfreebsd-gnu.ads +++ b/gcc/ada/s-osinte-kfreebsd-gnu.ads @@ -7,7 +7,7 @@ -- S p e c -- -- -- -- Copyright (C) 1991-1994, Florida State University -- --- Copyright (C) 1995-2015, Free Software Foundation, Inc. -- +-- Copyright (C) 1995-2016, Free Software Foundation, Inc. -- -- -- -- GNAT is free software; you can redistribute it and/or modify it under -- -- terms of the GNU General Public License as published by the Free Soft- -- @@ -216,6 +216,11 @@ package System.OS_Interface is return int; pragma Import (C, clock_gettime, "clock_gettime"); + function clock_getres + (clock_id : clockid_t; + res : access timespec) return int; + pragma Import (C, clock_getres, "clock_getres"); + function To_Duration (TS : timespec) return Duration; pragma Inline (To_Duration); @@ -330,8 +335,7 @@ package System.OS_Interface is -- returns the stack base of the specified thread. Only call this function -- when Stack_Base_Available is True. - function Get_Page_Size return size_t; - function Get_Page_Size return Address; + function Get_Page_Size return int; pragma Import (C, Get_Page_Size, "getpagesize"); -- Returns the size of a page diff --git a/gcc/ada/s-osinte-rtems.ads b/gcc/ada/s-osinte-rtems.ads index 5a143cc..a658bbe 100644 --- a/gcc/ada/s-osinte-rtems.ads +++ b/gcc/ada/s-osinte-rtems.ads @@ -6,7 +6,7 @@ -- -- -- S p e c -- -- -- --- Copyright (C) 1997-2011 Free Software Foundation, Inc. -- +-- Copyright (C) 1997-2016 Free Software Foundation, Inc. -- -- -- -- GNARL is free software; you can redistribute it and/or modify it under -- -- terms of the GNU General Public License as published by the Free Soft- -- @@ -188,6 +188,11 @@ package System.OS_Interface is tp : access timespec) return int; pragma Import (C, clock_gettime, "clock_gettime"); + function clock_getres + (clock_id : clockid_t; + res : access timespec) return int; + pragma Import (C, clock_getres, "clock_getres"); + function To_Duration (TS : timespec) return Duration; pragma Inline (To_Duration); @@ -291,8 +296,7 @@ package System.OS_Interface is -- These two functions are only needed to share s-taprop.adb with -- FSU threads. - function Get_Page_Size return size_t; - function Get_Page_Size return Address; + function Get_Page_Size return int; pragma Import (C, Get_Page_Size, "getpagesize"); -- Returns the size of a page diff --git a/gcc/alias.c b/gcc/alias.c index a0e25dc..ea226fc 100644 --- a/gcc/alias.c +++ b/gcc/alias.c @@ -769,6 +769,10 @@ reference_alias_ptr_type_1 (tree *t) tree reference_alias_ptr_type (tree t) { + /* If the frontend assigns this alias-set zero, preserve that. */ + if (lang_hooks.get_alias_set (t) == 0) + return ptr_type_node; + tree ptype = reference_alias_ptr_type_1 (&t); /* If there is a given pointer type for aliasing purposes, return it. */ if (ptype != NULL_TREE) diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index 1e7b27b..7b53889 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,25 @@ +2016-06-14 Jakub Jelinek + + Backported from mainline + 2016-06-10 Jakub Jelinek + + PR c/68657 + * c.opt (Wpsabi): Add Warning flag. + +2016-06-13 Jakub Jelinek + + PR sanitizer/71498 + * c-gimplify.c (ubsan_walk_array_refs_r): Set *walk_subtrees = 0 on + all BIND_EXPRs, and on all BIND_EXPRs recurse also on BIND_EXPR_BODY. + +2016-05-30 Jakub Jelinek + + PR c++/71349 + * c-omp.c (c_omp_split_clauses): Put OMP_CLAUSE_DEPEND to + C_OMP_CLAUSE_SPLIT_TARGET. Put OMP_CLAUSE_NOWAIT to + C_OMP_CLAUSE_SPLIT_TARGET if combined with target construct, + instead of C_OMP_CLAUSE_SPLIT_FOR. + 2016-04-29 Cesar Philippidis PR middle-end/70626 diff --git a/gcc/c-family/c-gimplify.c b/gcc/c-family/c-gimplify.c index 0757193..c18b057 100644 --- a/gcc/c-family/c-gimplify.c +++ b/gcc/c-family/c-gimplify.c @@ -67,23 +67,23 @@ ubsan_walk_array_refs_r (tree *tp, int *walk_subtrees, void *data) { hash_set *pset = (hash_set *) data; - /* Since walk_tree doesn't call the callback function on the decls - in BIND_EXPR_VARS, we have to walk them manually. */ if (TREE_CODE (*tp) == BIND_EXPR) { + /* Since walk_tree doesn't call the callback function on the decls + in BIND_EXPR_VARS, we have to walk them manually, so we can avoid + instrumenting DECL_INITIAL of TREE_STATIC vars. */ + *walk_subtrees = 0; for (tree decl = BIND_EXPR_VARS (*tp); decl; decl = DECL_CHAIN (decl)) { if (TREE_STATIC (decl)) - { - *walk_subtrees = 0; - continue; - } + continue; walk_tree (&DECL_INITIAL (decl), ubsan_walk_array_refs_r, pset, pset); walk_tree (&DECL_SIZE (decl), ubsan_walk_array_refs_r, pset, pset); walk_tree (&DECL_SIZE_UNIT (decl), ubsan_walk_array_refs_r, pset, pset); } + walk_tree (&BIND_EXPR_BODY (*tp), ubsan_walk_array_refs_r, pset, pset); } else if (TREE_CODE (*tp) == ADDR_EXPR && TREE_CODE (TREE_OPERAND (*tp, 0)) == ARRAY_REF) diff --git a/gcc/c-family/c-omp.c b/gcc/c-family/c-omp.c index be401bb..1691c40 100644 --- a/gcc/c-family/c-omp.c +++ b/gcc/c-family/c-omp.c @@ -983,6 +983,7 @@ c_omp_split_clauses (location_t loc, enum tree_code code, case OMP_CLAUSE_MAP: case OMP_CLAUSE_IS_DEVICE_PTR: case OMP_CLAUSE_DEFAULTMAP: + case OMP_CLAUSE_DEPEND: s = C_OMP_CLAUSE_SPLIT_TARGET; break; case OMP_CLAUSE_NUM_TEAMS: @@ -998,7 +999,6 @@ c_omp_split_clauses (location_t loc, enum tree_code code, s = C_OMP_CLAUSE_SPLIT_PARALLEL; break; case OMP_CLAUSE_ORDERED: - case OMP_CLAUSE_NOWAIT: s = C_OMP_CLAUSE_SPLIT_FOR; break; case OMP_CLAUSE_SCHEDULE: @@ -1333,6 +1333,18 @@ c_omp_split_clauses (location_t loc, enum tree_code code, else s = C_OMP_CLAUSE_SPLIT_FOR; break; + case OMP_CLAUSE_NOWAIT: + /* Nowait clause is allowed on target, for and sections, but + is not allowed on parallel for or parallel sections. Therefore, + put it on target construct if present, because that can only + be combined with parallel for{, simd} and not with for{, simd}, + otherwise to the worksharing construct. */ + if ((mask & (OMP_CLAUSE_MASK_1 << PRAGMA_OMP_CLAUSE_MAP)) + != 0) + s = C_OMP_CLAUSE_SPLIT_TARGET; + else + s = C_OMP_CLAUSE_SPLIT_FOR; + break; default: gcc_unreachable (); } diff --git a/gcc/c-family/c.opt b/gcc/c-family/c.opt index 4f86876..88038a0 100644 --- a/gcc/c-family/c.opt +++ b/gcc/c-family/c.opt @@ -265,7 +265,7 @@ C++ ObjC++ Var(warn_abi_tag) Warning Warn if a subobject has an abi_tag attribute that the complete object type does not have. Wpsabi -C ObjC C++ ObjC++ LTO Var(warn_psabi) Init(1) Undocumented LangEnabledBy(C ObjC C++ ObjC++,Wabi) +C ObjC C++ ObjC++ LTO Var(warn_psabi) Init(1) Warning Undocumented LangEnabledBy(C ObjC C++ ObjC++,Wabi) Waddress C ObjC C++ ObjC++ Var(warn_address) Warning LangEnabledBy(C ObjC C++ ObjC++,Wall) diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index 5be1b5f..7edb380 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,27 @@ +2016-06-10 Thomas Schwinge + + PR c/71381 + Backport from trunk r237290: + * c-parser.c (c_parser_omp_variable_list) : + Loosen checking. + +2016-05-30 Jakub Jelinek + + PR c++/71349 + * c-parser.c (c_parser_omp_for): Don't disallow nowait clause + when combined with target construct. + +2016-05-19 David Malcolm + + Backport from trunk r236488. + PR c/71171 + * c-parser.c (c_parser_generic_selection): Use c_expr::set_error + in error-handling. + (c_parser_postfix_expression): Likewise. + * c-tree.h (c_expr::set_error): New method. + * c-typeck.c (parser_build_binary_op): In error-handling, ensure + that result's range is initialized. + 2016-04-29 Cesar Philippidis PR middle-end/70626 diff --git a/gcc/c/c-parser.c b/gcc/c/c-parser.c index 17df493..c9eb8dd 100644 --- a/gcc/c/c-parser.c +++ b/gcc/c/c-parser.c @@ -7185,7 +7185,7 @@ c_parser_generic_selection (c_parser *parser) error_expr.original_code = ERROR_MARK; error_expr.original_type = NULL; - error_expr.value = error_mark_node; + error_expr.set_error (); matched_assoc.type_location = UNKNOWN_LOCATION; matched_assoc.type = NULL_TREE; matched_assoc.expression = error_expr; @@ -7496,13 +7496,13 @@ c_parser_postfix_expression (c_parser *parser) gcc_assert (c_dialect_objc ()); if (!c_parser_require (parser, CPP_DOT, "expected %<.%>")) { - expr.value = error_mark_node; + expr.set_error (); break; } if (c_parser_next_token_is_not (parser, CPP_NAME)) { c_parser_error (parser, "expected identifier"); - expr.value = error_mark_node; + expr.set_error (); break; } c_token *component_tok = c_parser_peek_token (parser); @@ -7516,7 +7516,7 @@ c_parser_postfix_expression (c_parser *parser) } default: c_parser_error (parser, "expected expression"); - expr.value = error_mark_node; + expr.set_error (); break; } break; @@ -7538,7 +7538,7 @@ c_parser_postfix_expression (c_parser *parser) parser->error = true; c_parser_skip_until_found (parser, CPP_CLOSE_BRACE, NULL); c_parser_skip_until_found (parser, CPP_CLOSE_PAREN, NULL); - expr.value = error_mark_node; + expr.set_error (); break; } stmt = c_begin_stmt_expr (); @@ -7567,7 +7567,7 @@ c_parser_postfix_expression (c_parser *parser) "expected %<)%>"); if (type_name == NULL) { - expr.value = error_mark_node; + expr.set_error (); } else expr = c_parser_postfix_expression_after_paren_type (parser, @@ -7627,7 +7627,7 @@ c_parser_postfix_expression (c_parser *parser) c_parser_consume_token (parser); if (!c_parser_require (parser, CPP_OPEN_PAREN, "expected %<(%>")) { - expr.value = error_mark_node; + expr.set_error (); break; } e1 = c_parser_expr_no_commas (parser, NULL); @@ -7636,7 +7636,7 @@ c_parser_postfix_expression (c_parser *parser) if (!c_parser_require (parser, CPP_COMMA, "expected %<,%>")) { c_parser_skip_until_found (parser, CPP_CLOSE_PAREN, NULL); - expr.value = error_mark_node; + expr.set_error (); break; } loc = c_parser_peek_token (parser)->location; @@ -7646,7 +7646,7 @@ c_parser_postfix_expression (c_parser *parser) "expected %<)%>"); if (t1 == NULL) { - expr.value = error_mark_node; + expr.set_error (); } else { @@ -7668,7 +7668,7 @@ c_parser_postfix_expression (c_parser *parser) c_parser_consume_token (parser); if (!c_parser_require (parser, CPP_OPEN_PAREN, "expected %<(%>")) { - expr.value = error_mark_node; + expr.set_error (); break; } t1 = c_parser_type_name (parser); @@ -7679,7 +7679,7 @@ c_parser_postfix_expression (c_parser *parser) if (parser->error) { c_parser_skip_until_found (parser, CPP_CLOSE_PAREN, NULL); - expr.value = error_mark_node; + expr.set_error (); break; } @@ -7768,7 +7768,7 @@ c_parser_postfix_expression (c_parser *parser) &cexpr_list, true, &close_paren_loc)) { - expr.value = error_mark_node; + expr.set_error (); break; } @@ -7776,7 +7776,7 @@ c_parser_postfix_expression (c_parser *parser) { error_at (loc, "wrong number of arguments to " "%<__builtin_choose_expr%>"); - expr.value = error_mark_node; + expr.set_error (); break; } @@ -7801,25 +7801,25 @@ c_parser_postfix_expression (c_parser *parser) c_parser_consume_token (parser); if (!c_parser_require (parser, CPP_OPEN_PAREN, "expected %<(%>")) { - expr.value = error_mark_node; + expr.set_error (); break; } t1 = c_parser_type_name (parser); if (t1 == NULL) { - expr.value = error_mark_node; + expr.set_error (); break; } if (!c_parser_require (parser, CPP_COMMA, "expected %<,%>")) { c_parser_skip_until_found (parser, CPP_CLOSE_PAREN, NULL); - expr.value = error_mark_node; + expr.set_error (); break; } t2 = c_parser_type_name (parser); if (t2 == NULL) { - expr.value = error_mark_node; + expr.set_error (); break; } { @@ -7831,7 +7831,7 @@ c_parser_postfix_expression (c_parser *parser) e2 = groktypename (t2, NULL, NULL); if (e1 == error_mark_node || e2 == error_mark_node) { - expr.value = error_mark_node; + expr.set_error (); break; } @@ -7856,14 +7856,14 @@ c_parser_postfix_expression (c_parser *parser) &cexpr_list, false, &close_paren_loc)) { - expr.value = error_mark_node; + expr.set_error (); break; } if (vec_safe_length (cexpr_list) != 2) { error_at (loc, "wrong number of arguments to " "%<__builtin_call_with_static_chain%>"); - expr.value = error_mark_node; + expr.set_error (); break; } @@ -7898,7 +7898,7 @@ c_parser_postfix_expression (c_parser *parser) &cexpr_list, false, &close_paren_loc)) { - expr.value = error_mark_node; + expr.set_error (); break; } @@ -7906,7 +7906,7 @@ c_parser_postfix_expression (c_parser *parser) { error_at (loc, "wrong number of arguments to " "%<__builtin_complex%>"); - expr.value = error_mark_node; + expr.set_error (); break; } @@ -7928,7 +7928,7 @@ c_parser_postfix_expression (c_parser *parser) { error_at (loc, "%<__builtin_complex%> operand " "not of real binary floating-point type"); - expr.value = error_mark_node; + expr.set_error (); break; } if (TYPE_MAIN_VARIANT (TREE_TYPE (e1_p->value)) @@ -7936,7 +7936,7 @@ c_parser_postfix_expression (c_parser *parser) { error_at (loc, "%<__builtin_complex%> operands of different types"); - expr.value = error_mark_node; + expr.set_error (); break; } pedwarn_c90 (loc, OPT_Wpedantic, @@ -7962,7 +7962,7 @@ c_parser_postfix_expression (c_parser *parser) &cexpr_list, false, &close_paren_loc)) { - expr.value = error_mark_node; + expr.set_error (); break; } @@ -7985,7 +7985,7 @@ c_parser_postfix_expression (c_parser *parser) { error_at (loc, "wrong number of arguments to " "%<__builtin_shuffle%>"); - expr.value = error_mark_node; + expr.set_error (); } set_c_expr_source_range (&expr, loc, close_paren_loc); break; @@ -7995,7 +7995,7 @@ c_parser_postfix_expression (c_parser *parser) c_parser_consume_token (parser); if (!c_parser_require (parser, CPP_OPEN_PAREN, "expected %<(%>")) { - expr.value = error_mark_node; + expr.set_error (); break; } { @@ -8012,14 +8012,14 @@ c_parser_postfix_expression (c_parser *parser) c_parser_consume_token (parser); if (!c_parser_require (parser, CPP_OPEN_PAREN, "expected %<(%>")) { - expr.value = error_mark_node; + expr.set_error (); break; } if (c_parser_next_token_is_not (parser, CPP_NAME)) { c_parser_error (parser, "expected identifier"); c_parser_skip_until_found (parser, CPP_CLOSE_PAREN, NULL); - expr.value = error_mark_node; + expr.set_error (); break; } { @@ -8038,13 +8038,13 @@ c_parser_postfix_expression (c_parser *parser) c_parser_consume_token (parser); if (!c_parser_require (parser, CPP_OPEN_PAREN, "expected %<(%>")) { - expr.value = error_mark_node; + expr.set_error (); break; } t1 = c_parser_type_name (parser); if (t1 == NULL) { - expr.value = error_mark_node; + expr.set_error (); c_parser_skip_until_found (parser, CPP_CLOSE_PAREN, NULL); break; } @@ -8067,7 +8067,7 @@ c_parser_postfix_expression (c_parser *parser) error_at (loc, "-fcilkplus must be enabled to use " "%<_Cilk_spawn%>"); expr = c_parser_cast_expression (parser, NULL); - expr.value = error_mark_node; + expr.set_error (); } else if (c_parser_peek_token (parser)->keyword == RID_CILK_SPAWN) { @@ -8086,7 +8086,7 @@ c_parser_postfix_expression (c_parser *parser) break; default: c_parser_error (parser, "expected expression"); - expr.value = error_mark_node; + expr.set_error (); break; } break; @@ -8107,7 +8107,7 @@ c_parser_postfix_expression (c_parser *parser) /* Else fall through to report error. */ default: c_parser_error (parser, "expected expression"); - expr.value = error_mark_node; + expr.set_error (); break; } return c_parser_postfix_expression_after_primary @@ -8325,7 +8325,7 @@ c_parser_postfix_expression_after_primary (c_parser *parser, else { c_parser_error (parser, "expected identifier"); - expr.value = error_mark_node; + expr.set_error (); expr.original_code = ERROR_MARK; expr.original_type = NULL; return expr; @@ -8357,7 +8357,7 @@ c_parser_postfix_expression_after_primary (c_parser *parser, else { c_parser_error (parser, "expected identifier"); - expr.value = error_mark_node; + expr.set_error (); expr.original_code = ERROR_MARK; expr.original_type = NULL; return expr; @@ -10595,6 +10595,8 @@ c_parser_omp_variable_list (c_parser *parser, switch (kind) { case OMP_CLAUSE__CACHE_: + /* The OpenACC cache directive explicitly only allows "array + elements or subarrays". */ if (c_parser_peek_token (parser)->type != CPP_OPEN_SQUARE) { c_parser_error (parser, "expected %<[%>"); @@ -10657,25 +10659,6 @@ c_parser_omp_variable_list (c_parser *parser, break; } - if (kind == OMP_CLAUSE__CACHE_) - { - if (TREE_CODE (low_bound) != INTEGER_CST - && !TREE_READONLY (low_bound)) - { - error_at (clause_loc, - "%qD is not a constant", low_bound); - t = error_mark_node; - } - - if (TREE_CODE (length) != INTEGER_CST - && !TREE_READONLY (length)) - { - error_at (clause_loc, - "%qD is not a constant", length); - t = error_mark_node; - } - } - t = tree_cons (low_bound, length, t); } break; @@ -15094,7 +15077,9 @@ c_parser_omp_for (location_t loc, c_parser *parser, strcat (p_name, " for"); mask |= OMP_FOR_CLAUSE_MASK; - if (cclauses) + /* parallel for{, simd} disallows nowait clause, but for + target {teams distribute ,}parallel for{, simd} it should be accepted. */ + if (cclauses && (mask & (OMP_CLAUSE_MASK_1 << PRAGMA_OMP_CLAUSE_MAP)) == 0) mask &= ~(OMP_CLAUSE_MASK_1 << PRAGMA_OMP_CLAUSE_NOWAIT); /* Composite distribute parallel for{, simd} disallows ordered clause. */ if ((mask & (OMP_CLAUSE_MASK_1 << PRAGMA_OMP_CLAUSE_DIST_SCHEDULE)) != 0) diff --git a/gcc/c/c-tree.h b/gcc/c/c-tree.h index d559207..bb12a20 100644 --- a/gcc/c/c-tree.h +++ b/gcc/c/c-tree.h @@ -143,6 +143,15 @@ struct c_expr of this expression. */ location_t get_start () const { return src_range.m_start; } location_t get_finish () const { return src_range.m_finish; } + + /* Set the value to error_mark_node whilst ensuring that src_range + is initialized. */ + void set_error () + { + value = error_mark_node; + src_range.m_start = UNKNOWN_LOCATION; + src_range.m_finish = UNKNOWN_LOCATION; + } }; /* Type alias for struct c_expr. This allows to use the structure diff --git a/gcc/c/c-typeck.c b/gcc/c/c-typeck.c index 59a3c61..8ad99d5 100644 --- a/gcc/c/c-typeck.c +++ b/gcc/c/c-typeck.c @@ -3530,7 +3530,12 @@ parser_build_binary_op (location_t location, enum tree_code code, result.original_type = NULL; if (TREE_CODE (result.value) == ERROR_MARK) - return result; + { + set_c_expr_source_range (&result, + arg1.get_start (), + arg2.get_finish ()); + return result; + } if (location != UNKNOWN_LOCATION) protected_set_expr_location (result.value, location); diff --git a/gcc/calls.c b/gcc/calls.c index 6415e08..6cc1fc7 100644 --- a/gcc/calls.c +++ b/gcc/calls.c @@ -1188,6 +1188,7 @@ initialize_argument_information (int num_actuals ATTRIBUTE_UNUSED, j--; } } + argpos = 0; FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) { tree argtype = TREE_TYPE (arg); @@ -1206,6 +1207,14 @@ initialize_argument_information (int num_actuals ATTRIBUTE_UNUSED, chkp_find_bound_slots (argtype, slots); } } + else if (CALL_WITH_BOUNDS_P (exp) + && pass_by_reference (NULL, TYPE_MODE (argtype), argtype, + argpos < n_named_args)) + { + if (slots) + BITMAP_FREE (slots); + ptr_arg = j; + } else if (POINTER_BOUNDS_TYPE_P (argtype)) { /* We expect bounds in instrumented calls only. @@ -1249,6 +1258,7 @@ initialize_argument_information (int num_actuals ATTRIBUTE_UNUSED, else args[j].tree_value = arg; j--; + argpos++; } if (slots) diff --git a/gcc/cgraph.c b/gcc/cgraph.c index 4804081..ed9f841 100644 --- a/gcc/cgraph.c +++ b/gcc/cgraph.c @@ -1504,10 +1504,21 @@ cgraph_edge::redirect_call_stmt_to_callee (void) update_stmt_fn (DECL_STRUCT_FUNCTION (e->caller->decl), new_stmt); } + /* If changing the call to __cxa_pure_virtual or similar noreturn function, + adjust gimple_call_fntype too. */ + if (gimple_call_noreturn_p (new_stmt) + && VOID_TYPE_P (TREE_TYPE (TREE_TYPE (e->callee->decl))) + && TYPE_ARG_TYPES (TREE_TYPE (e->callee->decl)) + && (TREE_VALUE (TYPE_ARG_TYPES (TREE_TYPE (e->callee->decl))) + == void_type_node)) + gimple_call_set_fntype (new_stmt, TREE_TYPE (e->callee->decl)); + /* If the call becomes noreturn, remove the LHS if possible. */ if (lhs && (gimple_call_flags (new_stmt) & ECF_NORETURN) - && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (lhs))) == INTEGER_CST) + && (VOID_TYPE_P (TREE_TYPE (gimple_call_fntype (new_stmt))) + || (TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (lhs))) == INTEGER_CST + && !TREE_ADDRESSABLE (TREE_TYPE (lhs))))) { if (TREE_CODE (lhs) == SSA_NAME) { diff --git a/gcc/config.gcc b/gcc/config.gcc index 9d27dc4..1f3da54 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -1058,11 +1058,9 @@ arm*-*-freebsd*) # ARM FreeBSD EABI case $target in armv6*-*-freebsd*) tm_defines="${tm_defines} TARGET_FREEBSD_ARMv6=1" - ;; - esac - case $target in - arm*hf-*-freebsd*) - tm_defines="${tm_defines} TARGET_FREEBSD_ARM_HARD_FLOAT=1" + if test $fbsd_major -ge 11; then + tm_defines="${tm_defines} TARGET_FREEBSD_ARM_HARD_FLOAT=1" + fi ;; esac with_tls=${with_tls:-gnu} @@ -4282,9 +4280,9 @@ case "${target}" in esac ;; sparc*-*-*) - supported_defaults="cpu float tune" + supported_defaults="cpu cpu_32 cpu_64 float tune tune_32 tune_64" - for which in cpu tune; do + for which in cpu cpu_32 cpu_64 tune tune_32 tune_64; do eval "val=\$with_$which" case ${val} in "" | sparc | sparcv9 | sparc64 \ @@ -4293,7 +4291,7 @@ case "${target}" in | sparclite | f930 | f934 | sparclite86x \ | sparclet | tsc701 \ | v9 | ultrasparc | ultrasparc3 | niagara | niagara2 \ - | niagara3 | niagara4) + | niagara3 | niagara4 | niagara7) # OK ;; *) diff --git a/gcc/config.in b/gcc/config.in index 115cb61..86bd5b0 100644 --- a/gcc/config.in +++ b/gcc/config.in @@ -622,6 +622,12 @@ #endif +/* Define if your assembler supports SPARC5 and VIS 4.0 instructions. */ +#ifndef USED_FOR_TARGET +#undef HAVE_AS_SPARC5_VIS4 +#endif + + /* Define if your assembler and linker support GOTDATA_OP relocs. */ #ifndef USED_FOR_TARGET #undef HAVE_AS_SPARC_GOTDATA_OP diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 0e4a0a7..6ea35bf 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1919,16 +1919,6 @@ } ) -(define_insn "aarch64_vmls" - [(set (match_operand:VDQF 0 "register_operand" "=w") - (minus:VDQF (match_operand:VDQF 1 "register_operand" "0") - (mult:VDQF (match_operand:VDQF 2 "register_operand" "w") - (match_operand:VDQF 3 "register_operand" "w"))))] - "TARGET_SIMD" - "fmls\\t%0., %2., %3." - [(set_attr "type" "neon_fp_mla__scalar")] -) - ;; FP Max/Min ;; Max/Min are introduced by idiom recognition by GCC's mid-end. An ;; expression like: diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 932608b..3e4594b 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -3738,7 +3738,8 @@ ;; BUGCHK is documented common to OSF/1 and VMS PALcode. (define_insn "trap" - [(trap_if (const_int 1) (const_int 0))] + [(trap_if (const_int 1) (const_int 0)) + (use (reg:DI 29))] "" "call_pal 0x81" [(set_attr "type" "callpal")]) @@ -5157,7 +5158,7 @@ "TARGET_ABI_OSF" { if (TARGET_EXPLICIT_RELOCS) - return "ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"; + return "#"; else return "ldgp $29,0($26)"; } diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 90fb40f..68b2839 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -2861,6 +2861,10 @@ arm_builtin_vectorized_function (unsigned int fn, tree type_out, tree type_in) int in_n, out_n; bool out_unsigned_p = TYPE_UNSIGNED (type_out); + /* Can't provide any vectorized builtins when we can't use NEON. */ + if (!TARGET_NEON) + return NULL_TREE; + if (TREE_CODE (type_out) != VECTOR_TYPE || TREE_CODE (type_in) != VECTOR_TYPE) return NULL_TREE; @@ -2875,7 +2879,7 @@ arm_builtin_vectorized_function (unsigned int fn, tree type_out, tree type_in) NULL_TREE is returned if no such builtin is available. */ #undef ARM_CHECK_BUILTIN_MODE #define ARM_CHECK_BUILTIN_MODE(C) \ - (TARGET_NEON && TARGET_FPU_ARMV8 \ + (TARGET_FPU_ARMV8 \ && flag_unsafe_math_optimizations \ && ARM_CHECK_BUILTIN_MODE_1 (C)) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 3d4c27c..32accc9 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -17759,6 +17759,7 @@ arm_output_multireg_pop (rtx *operands, bool return_pc, rtx cond, bool reverse, int num_saves = XVECLEN (operands[0], 0); unsigned int regno; unsigned int regno_base = REGNO (operands[1]); + bool interrupt_p = IS_INTERRUPT (arm_current_func_type ()); offset = 0; offset += update ? 1 : 0; @@ -17776,20 +17777,16 @@ arm_output_multireg_pop (rtx *operands, bool return_pc, rtx cond, bool reverse, } conditional = reverse ? "%?%D0" : "%?%d0"; - if ((regno_base == SP_REGNUM) && update) - { - sprintf (pattern, "pop%s\t{", conditional); - } + /* Can't use POP if returning from an interrupt. */ + if ((regno_base == SP_REGNUM) && update && !(interrupt_p && return_pc)) + sprintf (pattern, "pop%s\t{", conditional); else { /* Output ldmfd when the base register is SP, otherwise output ldmia. It's just a convention, their semantics are identical. */ if (regno_base == SP_REGNUM) - /* update is never true here, hence there is no need to handle - pop here. */ - sprintf (pattern, "ldmfd%s", conditional); - - if (update) + sprintf (pattern, "ldmfd%s\t", conditional); + else if (update) sprintf (pattern, "ldmia%s\t", conditional); else sprintf (pattern, "ldm%s\t", conditional); @@ -17815,7 +17812,7 @@ arm_output_multireg_pop (rtx *operands, bool return_pc, rtx cond, bool reverse, strcat (pattern, "}"); - if (IS_INTERRUPT (arm_current_func_type ()) && return_pc) + if (interrupt_p && return_pc) strcat (pattern, "^"); output_asm_insn (pattern, &cond); @@ -19626,8 +19623,12 @@ output_return_instruction (rtx operand, bool really_return, bool reverse, sprintf (instr, "ldmfd%s\t%%|sp, {", conditional); } } + /* For interrupt returns we have to use an LDM rather than + a POP so that we can use the exception return variant. */ + else if (IS_INTERRUPT (func_type)) + sprintf (instr, "ldmfd%s\t%%|sp!, {", conditional); else - sprintf (instr, "pop%s\t{", conditional); + sprintf (instr, "pop%s\t{", conditional); p = instr + strlen (instr); @@ -21465,7 +21466,11 @@ arm_expand_prologue (void) /* Naked functions don't have prologues. */ if (IS_NAKED (func_type)) - return; + { + if (flag_stack_usage_info) + current_function_static_stack_size = 0; + return; + } /* Make a copy of c_f_p_a_s as we may need to modify it locally. */ args_to_push = crtl->args.pretend_args_size; @@ -24719,7 +24724,11 @@ thumb1_expand_prologue (void) /* Naked functions don't have prologues. */ if (IS_NAKED (func_type)) - return; + { + if (flag_stack_usage_info) + current_function_static_stack_size = 0; + return; + } if (IS_INTERRUPT (func_type)) { diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index afdc546..1a4c701 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -141,8 +141,12 @@ "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS" "@internal Any x87 register when 80387 FP arithmetic is enabled.") +;; Yr constraint is meant to be used in noavx contexts only, for VEX and EVEX +;; the lower register numbers need the same instruction sizes as any other. +;; In case Yr constraint is misused, try to limit the damage, by treating +;; it as x constraint in avx mode, not v constraint. (define_register_constraint "Yr" - "TARGET_SSE ? (X86_TUNE_AVOID_4BYTE_PREFIXES ? NO_REX_SSE_REGS : ALL_SSE_REGS) : NO_REGS" + "TARGET_SSE ? ((TARGET_AVOID_4BYTE_PREFIXES && !TARGET_AVX) ? NO_REX_SSE_REGS : SSE_REGS) : NO_REGS" "@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.") ;; We use the B prefix to denote any number of internal operands: diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index b121466..a9d5135 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -637,33 +637,27 @@ const char *host_detect_local_cpu (int argc, const char **argv) } else if (vendor == signature_CENTAUR_ebx) { - if (arch) + processor = PROCESSOR_GENERIC; + + switch (family) { - switch (family) - { - case 6: - if (model > 9) - /* Use the default detection procedure. */ - processor = PROCESSOR_GENERIC; - else if (model == 9) - cpu = "c3-2"; - else if (model >= 6) - cpu = "c3"; - else - processor = PROCESSOR_GENERIC; - break; - case 5: - if (has_3dnow) - cpu = "winchip2"; - else if (has_mmx) - cpu = "winchip2-c6"; - else - processor = PROCESSOR_GENERIC; - break; - default: - /* We have no idea. */ - processor = PROCESSOR_GENERIC; - } + default: + /* We have no idea. */ + break; + + case 5: + if (has_3dnow || has_mmx) + processor = PROCESSOR_I486; + break; + + case 6: + if (model > 9 || has_longmode) + /* Use the default detection procedure. */ + ; + else if (model == 9) + processor = PROCESSOR_PENTIUMPRO; + else if (model >= 6) + processor = PROCESSOR_I486; } } else @@ -694,7 +688,18 @@ const char *host_detect_local_cpu (int argc, const char **argv) /* Default. */ break; case PROCESSOR_I486: - cpu = "i486"; + if (arch && vendor == signature_CENTAUR_ebx) + { + if (model >= 6) + cpu = "c3"; + else if (has_3dnow) + cpu = "winchip2"; + else + /* Assume WinChip C6. */ + cpu = "winchip-c6"; + } + else + cpu = "i486"; break; case PROCESSOR_PENTIUM: if (arch && has_mmx) @@ -817,8 +822,13 @@ const char *host_detect_local_cpu (int argc, const char **argv) /* It is Pentium M. */ cpu = "pentium-m"; else if (has_sse) - /* It is Pentium III. */ - cpu = "pentium3"; + { + if (vendor == signature_CENTAUR_ebx) + cpu = "c3-2"; + else + /* It is Pentium III. */ + cpu = "pentium3"; + } else if (has_mmx) /* It is Pentium II. */ cpu = "pentium2"; @@ -902,6 +912,11 @@ const char *host_detect_local_cpu (int argc, const char **argv) else cpu = "prescott"; } + else if (has_longmode) + /* Perhaps some emulator? Assume x86-64, otherwise gcc + -march=native would be unusable for 64-bit compilations, + as all the CPUs below are 32-bit only. */ + cpu = "x86-64"; else if (has_sse2) cpu = "pentium4"; else if (has_cmov) diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index b892f08..86139db4 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -292,6 +292,7 @@ DEF_FUNCTION_TYPE (V8DF, V4DF) DEF_FUNCTION_TYPE (V8DF, V2DF) DEF_FUNCTION_TYPE (V16SI, V4SI) DEF_FUNCTION_TYPE (V16SI, V8SI) +DEF_FUNCTION_TYPE (V16SI, V16SF) DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, UHI) DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, UQI) DEF_FUNCTION_TYPE (V8DI, PV8DI) @@ -1035,14 +1036,17 @@ DEF_FUNCTION_TYPE (VOID, QI, V8DI, PCINT, INT, INT) DEF_FUNCTION_TYPE_ALIAS (V2DF_FTYPE_V2DF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V4DF_FTYPE_V4DF, ROUND) +DEF_FUNCTION_TYPE_ALIAS (V8DF_FTYPE_V8DF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V4SF_FTYPE_V4SF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V8SF_FTYPE_V8SF, ROUND) +DEF_FUNCTION_TYPE_ALIAS (V16SF_FTYPE_V16SF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V4SI_FTYPE_V2DF_V2DF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V8SI_FTYPE_V4DF_V4DF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V16SI_FTYPE_V8DF_V8DF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V4SI_FTYPE_V4SF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V8SI_FTYPE_V8SF, ROUND) +DEF_FUNCTION_TYPE_ALIAS (V16SI_FTYPE_V16SF, ROUND) DEF_FUNCTION_TYPE_ALIAS (INT_FTYPE_V2DF_V2DF, PTEST) DEF_FUNCTION_TYPE_ALIAS (INT_FTYPE_V2DI_V2DI, PTEST) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index f5d095c..cb4bd8f 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -18895,7 +18895,7 @@ ix86_avx256_split_vector_move_misalign (rtx op0, rtx op1) m = adjust_address (op0, mode, 0); emit_insn (extract (m, op1, const0_rtx)); m = adjust_address (op0, mode, 16); - emit_insn (extract (m, op1, const1_rtx)); + emit_insn (extract (m, copy_rtx (op1), const1_rtx)); } else emit_insn (store_unaligned (op0, op1)); @@ -19203,7 +19203,7 @@ ix86_expand_vector_move_misalign (machine_mode mode, rtx operands[]) m = adjust_address (op0, V2SFmode, 0); emit_insn (gen_sse_storelps (m, op1)); m = adjust_address (op0, V2SFmode, 8); - emit_insn (gen_sse_storehps (m, op1)); + emit_insn (gen_sse_storehps (m, copy_rtx (op1))); } } } @@ -30686,7 +30686,7 @@ enum ix86_builtins IX86_BUILTIN_CVTPD2PS512, IX86_BUILTIN_CVTPD2UDQ512, IX86_BUILTIN_CVTPH2PS512, - IX86_BUILTIN_CVTPS2DQ512, + IX86_BUILTIN_CVTPS2DQ512_MASK, IX86_BUILTIN_CVTPS2PD512, IX86_BUILTIN_CVTPS2PH512, IX86_BUILTIN_CVTPS2UDQ512, @@ -32126,14 +32126,25 @@ enum ix86_builtins IX86_BUILTIN_COPYSIGNQ, /* Vectorizer support builtins. */ - IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, IX86_BUILTIN_CPYSGNPS, IX86_BUILTIN_CPYSGNPD, IX86_BUILTIN_CPYSGNPS256, IX86_BUILTIN_CPYSGNPS512, IX86_BUILTIN_CPYSGNPD256, IX86_BUILTIN_CPYSGNPD512, + IX86_BUILTIN_FLOORPS512, + IX86_BUILTIN_FLOORPD512, + IX86_BUILTIN_CEILPS512, + IX86_BUILTIN_CEILPD512, + IX86_BUILTIN_TRUNCPS512, + IX86_BUILTIN_TRUNCPD512, + IX86_BUILTIN_CVTPS2DQ512, + IX86_BUILTIN_VEC_PACK_SFIX512, + IX86_BUILTIN_FLOORPS_SFIX512, IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, + IX86_BUILTIN_CEILPS_SFIX512, + IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, + IX86_BUILTIN_ROUNDPS_AZ_SFIX512, IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, @@ -33948,6 +33959,17 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF }, { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundps512, "__builtin_ia32_floorps512", IX86_BUILTIN_FLOORPS512, (enum rtx_code) ROUND_FLOOR, (int) V16SF_FTYPE_V16SF_ROUND }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundps512, "__builtin_ia32_ceilps512", IX86_BUILTIN_CEILPS512, (enum rtx_code) ROUND_CEIL, (int) V16SF_FTYPE_V16SF_ROUND }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundps512, "__builtin_ia32_truncps512", IX86_BUILTIN_TRUNCPS512, (enum rtx_code) ROUND_TRUNC, (int) V16SF_FTYPE_V16SF_ROUND }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd512, "__builtin_ia32_floorpd512", IX86_BUILTIN_FLOORPD512, (enum rtx_code) ROUND_FLOOR, (int) V8DF_FTYPE_V8DF_ROUND }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd512, "__builtin_ia32_ceilpd512", IX86_BUILTIN_CEILPD512, (enum rtx_code) ROUND_CEIL, (int) V8DF_FTYPE_V8DF_ROUND }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd512, "__builtin_ia32_truncpd512", IX86_BUILTIN_TRUNCPD512, (enum rtx_code) ROUND_TRUNC, (int) V8DF_FTYPE_V8DF_ROUND }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si, "__builtin_ia32_cvtps2dq512", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_pack_sfix_v8df, "__builtin_ia32_vec_pack_sfix512", IX86_BUILTIN_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv16sf2_sfix, "__builtin_ia32_roundps_az_sfix512", IX86_BUILTIN_ROUNDPS_AZ_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V16SF }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundps512_sfix, "__builtin_ia32_floorps_sfix512", IX86_BUILTIN_FLOORPS_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V16SF_ROUND }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundps512_sfix, "__builtin_ia32_ceilps_sfix512", IX86_BUILTIN_CEILPS_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V16SF_ROUND }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND }, @@ -34864,7 +34886,7 @@ static const struct builtin_description bdesc_round_args[] = { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT }, - { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT }, @@ -38441,10 +38463,13 @@ ix86_expand_args_builtin (const struct builtin_description *d, { case V2DF_FTYPE_V2DF_ROUND: case V4DF_FTYPE_V4DF_ROUND: + case V8DF_FTYPE_V8DF_ROUND: case V4SF_FTYPE_V4SF_ROUND: case V8SF_FTYPE_V8SF_ROUND: + case V16SF_FTYPE_V16SF_ROUND: case V4SI_FTYPE_V4SF_ROUND: case V8SI_FTYPE_V8SF_ROUND: + case V16SI_FTYPE_V16SF_ROUND: return ix86_expand_sse_round (d, exp, target); case V4SI_FTYPE_V2DF_V2DF_ROUND: case V8SI_FTYPE_V4DF_V4DF_ROUND: @@ -38558,6 +38583,7 @@ ix86_expand_args_builtin (const struct builtin_description *d, case V16SI_FTYPE_V8SI: case V16SF_FTYPE_V4SF: case V16SI_FTYPE_V4SI: + case V16SI_FTYPE_V16SF: case V16SF_FTYPE_V16SF: case V8DI_FTYPE_UQI: case V8DF_FTYPE_V4DF: @@ -42263,6 +42289,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_FLOORPS_SFIX); else if (out_n == 8 && in_n == 8) return ix86_get_builtin (IX86_BUILTIN_FLOORPS_SFIX256); + else if (out_n == 16 && in_n == 16) + return ix86_get_builtin (IX86_BUILTIN_FLOORPS_SFIX512); } break; @@ -42288,6 +42316,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_CEILPS_SFIX); else if (out_n == 8 && in_n == 8) return ix86_get_builtin (IX86_BUILTIN_CEILPS_SFIX256); + else if (out_n == 16 && in_n == 16) + return ix86_get_builtin (IX86_BUILTIN_CEILPS_SFIX512); } break; @@ -42300,6 +42330,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_VEC_PACK_SFIX); else if (out_n == 8 && in_n == 4) return ix86_get_builtin (IX86_BUILTIN_VEC_PACK_SFIX256); + else if (out_n == 16 && in_n == 8) + return ix86_get_builtin (IX86_BUILTIN_VEC_PACK_SFIX512); } if (out_mode == SImode && in_mode == SFmode) { @@ -42307,6 +42339,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_CVTPS2DQ); else if (out_n == 8 && in_n == 8) return ix86_get_builtin (IX86_BUILTIN_CVTPS2DQ256); + else if (out_n == 16 && in_n == 16) + return ix86_get_builtin (IX86_BUILTIN_CVTPS2DQ512); } break; @@ -42332,6 +42366,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_ROUNDPS_AZ_SFIX); else if (out_n == 8 && in_n == 8) return ix86_get_builtin (IX86_BUILTIN_ROUNDPS_AZ_SFIX256); + else if (out_n == 16 && in_n == 16) + return ix86_get_builtin (IX86_BUILTIN_ROUNDPS_AZ_SFIX512); } break; @@ -42346,6 +42382,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_FLOORPD); else if (out_n == 4 && in_n == 4) return ix86_get_builtin (IX86_BUILTIN_FLOORPD256); + else if (out_n == 8 && in_n == 8) + return ix86_get_builtin (IX86_BUILTIN_FLOORPD512); } if (out_mode == SFmode && in_mode == SFmode) { @@ -42353,6 +42391,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_FLOORPS); else if (out_n == 8 && in_n == 8) return ix86_get_builtin (IX86_BUILTIN_FLOORPS256); + else if (out_n == 16 && in_n == 16) + return ix86_get_builtin (IX86_BUILTIN_FLOORPS512); } break; @@ -42367,6 +42407,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_CEILPD); else if (out_n == 4 && in_n == 4) return ix86_get_builtin (IX86_BUILTIN_CEILPD256); + else if (out_n == 8 && in_n == 8) + return ix86_get_builtin (IX86_BUILTIN_CEILPD512); } if (out_mode == SFmode && in_mode == SFmode) { @@ -42374,6 +42416,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_CEILPS); else if (out_n == 8 && in_n == 8) return ix86_get_builtin (IX86_BUILTIN_CEILPS256); + else if (out_n == 16 && in_n == 16) + return ix86_get_builtin (IX86_BUILTIN_CEILPS512); } break; @@ -42388,6 +42432,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_TRUNCPD); else if (out_n == 4 && in_n == 4) return ix86_get_builtin (IX86_BUILTIN_TRUNCPD256); + else if (out_n == 8 && in_n == 8) + return ix86_get_builtin (IX86_BUILTIN_TRUNCPD512); } if (out_mode == SFmode && in_mode == SFmode) { @@ -42395,6 +42441,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_TRUNCPS); else if (out_n == 8 && in_n == 8) return ix86_get_builtin (IX86_BUILTIN_TRUNCPS256); + else if (out_n == 16 && in_n == 16) + return ix86_get_builtin (IX86_BUILTIN_TRUNCPS512); } break; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index d0b418b..ec306f3 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -465,6 +465,8 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST]; ix86_tune_features[X86_TUNE_SLOW_PSHUFB] #define TARGET_VECTOR_PARALLEL_EXECUTION \ ix86_tune_features[X86_TUNE_VECTOR_PARALLEL_EXECUTION] +#define TARGET_AVOID_4BYTE_PREFIXES \ + ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES] #define TARGET_FUSE_CMP_AND_BRANCH_32 \ ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] #define TARGET_FUSE_CMP_AND_BRANCH_64 \ diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index cf29e5d..b1780a7 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -9332,7 +9332,7 @@ }) (define_split - [(set (match_operand:SF 0 "register_operand") + [(set (match_operand:SF 0 "general_reg_operand") (match_operator:SF 1 "absneg_operator" [(match_dup 0)])) (use (match_operand:V4SF 2)) (clobber (reg:CC FLAGS_REG))] @@ -9356,7 +9356,7 @@ }) (define_split - [(set (match_operand:DF 0 "register_operand") + [(set (match_operand:DF 0 "general_reg_operand") (match_operator:DF 1 "absneg_operator" [(match_dup 0)])) (use (match_operand 2)) (clobber (reg:CC FLAGS_REG))] @@ -9394,7 +9394,7 @@ }) (define_split - [(set (match_operand:XF 0 "register_operand") + [(set (match_operand:XF 0 "general_reg_operand") (match_operator:XF 1 "absneg_operator" [(match_dup 0)])) (use (match_operand 2)) (clobber (reg:CC FLAGS_REG))] @@ -11078,20 +11078,19 @@ (const_int 1)) (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT && !TARGET_USE_BT" - [(const_int 0)] + [(parallel [(set (match_dup 0) + (ior:DI (match_dup 0) (match_dup 3))) + (clobber (reg:CC FLAGS_REG))])] { int i = INTVAL (operands[1]); - rtx op1 = gen_int_mode (HOST_WIDE_INT_1U << i, DImode); + operands[3] = gen_int_mode (HOST_WIDE_INT_1U << i, DImode); - if (i >= 31) + if (!x86_64_immediate_operand (operands[3], DImode)) { - emit_move_insn (operands[2], op1); - op1 = operands[2]; + emit_move_insn (operands[2], operands[3]); + operands[3] = operands[2]; } - - emit_insn (gen_iordi3 (operands[0], operands[0], op1)); - DONE; }) (define_peephole2 @@ -11103,20 +11102,19 @@ (const_int 0)) (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT && !TARGET_USE_BT" - [(const_int 0)] + [(parallel [(set (match_dup 0) + (and:DI (match_dup 0) (match_dup 3))) + (clobber (reg:CC FLAGS_REG))])] { int i = INTVAL (operands[1]); - rtx op1 = gen_int_mode (HOST_WIDE_INT_1U << i, DImode); + operands[3] = gen_int_mode (~(HOST_WIDE_INT_1U << i), DImode); - if (i >= 32) + if (!x86_64_immediate_operand (operands[3], DImode)) { - emit_move_insn (operands[2], op1); - op1 = operands[2]; + emit_move_insn (operands[2], operands[3]); + operands[3] = operands[2]; } - - emit_insn (gen_anddi3 (operands[0], operands[0], op1)); - DONE; }) (define_peephole2 @@ -11129,20 +11127,19 @@ (match_dup 0) (const_int 1) (match_dup 1)))) (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT && !TARGET_USE_BT" - [(const_int 0)] + [(parallel [(set (match_dup 0) + (xor:DI (match_dup 0) (match_dup 3))) + (clobber (reg:CC FLAGS_REG))])] { int i = INTVAL (operands[1]); - rtx op1 = gen_int_mode (HOST_WIDE_INT_1U << i, DImode); + operands[3] = gen_int_mode (HOST_WIDE_INT_1U << i, DImode); - if (i >= 31) + if (!x86_64_immediate_operand (operands[3], DImode)) { - emit_move_insn (operands[2], op1); - op1 = operands[2]; + emit_move_insn (operands[2], operands[3]); + operands[3] = operands[2]; } - - emit_insn (gen_xordi3 (operands[0], operands[0], op1)); - DONE; }) (define_insn "*bt" diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a30b0b8..42506ef 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4488,7 +4488,7 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "")]) -(define_insn "avx512f_fix_notruncv16sfv16si" +(define_insn "avx512f_fix_notruncv16sfv16si" [(set (match_operand:V16SI 0 "register_operand" "=v") (unspec:V16SI [(match_operand:V16SF 1 "" "")] @@ -5046,7 +5046,7 @@ (set_attr "ssememalign" "64") (set_attr "mode" "V2DF")]) -(define_insn "avx512f_cvtpd2dq512" +(define_insn "avx512f_cvtpd2dq512" [(set (match_operand:V8SI 0 "register_operand" "=v") (unspec:V8SI [(match_operand:V8DF 1 "" "")] @@ -6006,6 +6006,23 @@ DONE; }) +(define_expand "avx512f_vec_pack_sfix_v8df" + [(match_operand:V16SI 0 "register_operand") + (match_operand:V8DF 1 "nonimmediate_operand") + (match_operand:V8DF 2 "nonimmediate_operand")] + "TARGET_AVX512F" +{ + rtx r1, r2; + + r1 = gen_reg_rtx (V8SImode); + r2 = gen_reg_rtx (V8SImode); + + emit_insn (gen_avx512f_cvtpd2dq512 (r1, operands[1])); + emit_insn (gen_avx512f_cvtpd2dq512 (r2, operands[2])); + emit_insn (gen_avx_vec_concatv16si (operands[0], r1, r2)); + DONE; +}) + (define_expand "vec_pack_sfix_v4df" [(match_operand:V8SI 0 "register_operand") (match_operand:V4DF 1 "nonimmediate_operand") @@ -15247,13 +15264,25 @@ DONE; }) -(define_expand "avx512f_roundpd512" - [(match_operand:V8DF 0 "register_operand") - (match_operand:V8DF 1 "nonimmediate_operand") +(define_expand "avx512f_round512" + [(match_operand:VF_512 0 "register_operand") + (match_operand:VF_512 1 "nonimmediate_operand") + (match_operand:SI 2 "const_0_to_15_operand")] + "TARGET_AVX512F" +{ + emit_insn (gen_avx512f_rndscale (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "avx512f_roundps512_sfix" + [(match_operand:V16SI 0 "register_operand") + (match_operand:V16SF 1 "nonimmediate_operand") (match_operand:SI 2 "const_0_to_15_operand")] "TARGET_AVX512F" { - emit_insn (gen_avx512f_rndscalev8df (operands[0], operands[1], operands[2])); + rtx tmp = gen_reg_rtx (V16SFmode); + emit_insn (gen_avx512f_rndscalev16sf (tmp, operands[1], operands[2])); + emit_insn (gen_fix_truncv16sfv16si2 (operands[0], tmp)); DONE; }) @@ -15353,7 +15382,7 @@ (define_expand "round2_sfix" [(match_operand: 0 "register_operand") - (match_operand:VF1_128_256 1 "register_operand")] + (match_operand:VF1 1 "register_operand")] "TARGET_ROUND && !flag_trapping_math" { rtx tmp = gen_reg_rtx (mode); diff --git a/gcc/config/microblaze/rtems.h b/gcc/config/microblaze/rtems.h index 68aa381..56f3f70 100644 --- a/gcc/config/microblaze/rtems.h +++ b/gcc/config/microblaze/rtems.h @@ -23,3 +23,10 @@ along with GCC; see the file COPYING3. If not see builtin_define( "__rtems__" ); \ builtin_assert( "system=rtems" ); \ } while (0) + +/* Redefine to include only items relevant for RTEMS */ +#undef LINK_SPEC +#define LINK_SPEC "%{shared:-shared} -N -relax \ + %{mbig-endian:-EB --oformat=elf32-microblaze} \ + %{mlittle-endian:-EL --oformat=elf32-microblazeel} \ + %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0}" diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c index b088cf8..a6c90b6 100644 --- a/gcc/config/nvptx/nvptx.c +++ b/gcc/config/nvptx/nvptx.c @@ -483,7 +483,7 @@ nvptx_strict_argument_naming (cumulative_args_t cum_v) static rtx nvptx_libcall_value (machine_mode mode, const_rtx) { - if (!cfun->machine->doing_call) + if (!cfun || !cfun->machine->doing_call) /* Pretend to return in a hard reg for early uses before pseudos can be generated. */ return gen_rtx_REG (mode, NVPTX_RETURN_REGNUM); @@ -502,6 +502,7 @@ nvptx_function_value (const_tree type, const_tree ARG_UNUSED (func), if (outgoing) { + gcc_assert (cfun); cfun->machine->return_mode = mode; return gen_rtx_REG (mode, NVPTX_RETURN_REGNUM); } diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index ea6af8d..f9fac68 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -327,8 +327,8 @@ #define vec_sqrt __builtin_vec_sqrt #define vec_vsx_ld __builtin_vec_vsx_ld #define vec_vsx_st __builtin_vec_vsx_st -#define vec_xl __builtin_vec_vsx_ld -#define vec_xst __builtin_vec_vsx_st +#define vec_xl __builtin_vec_xl +#define vec_xst __builtin_vec_xst /* Note, xxsldi and xxpermdi were added as __builtin_vsx_ functions instead of __builtin_vec_ */ @@ -384,6 +384,23 @@ #define vec_vupklsw __builtin_vec_vupklsw #endif +#ifdef _ARCH_PWR9 +/* Vector additions added in ISA 3.0. */ +#define vec_vctz __builtin_vec_vctz +#define vec_cntlz __builtin_vec_vctz +#define vec_vctzb __builtin_vec_vctzb +#define vec_vctzd __builtin_vec_vctzd +#define vec_vctzh __builtin_vec_vctzh +#define vec_vctzw __builtin_vec_vctzw +#define vec_vprtyb __builtin_vec_vprtyb +#define vec_vprtybd __builtin_vec_vprtybd +#define vec_vprtybw __builtin_vec_vprtybw + +#ifdef _ARCH_PPC64 +#define vec_vprtybq __builtin_vec_vprtybq +#endif +#endif + /* Predicates. For C++, we use templates in order to allow non-parenthesized arguments. For C, instead, we use macros since non-parenthesized arguments were diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 9c3084d..3707091 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -58,6 +58,7 @@ UNSPEC_VSUM2SWS UNSPEC_VSUMSWS UNSPEC_VPERM + UNSPEC_VPERMR UNSPEC_VPERM_UNS UNSPEC_VRFIN UNSPEC_VCFUX @@ -73,6 +74,9 @@ UNSPEC_VUNPACK_LO_SIGN_DIRECT UNSPEC_VUPKHPX UNSPEC_VUPKLPX + UNSPEC_DARN + UNSPEC_DARN_32 + UNSPEC_DARN_RAW UNSPEC_DST UNSPEC_DSTT UNSPEC_DSTST @@ -189,6 +193,13 @@ (KF "FLOAT128_VECTOR_P (KFmode)") (TF "FLOAT128_VECTOR_P (TFmode)")]) +;; Specific iterator for parity which does not have a byte/half-word form, but +;; does have a quad word form +(define_mode_iterator VParity [V4SI + V2DI + V1TI + (TI "TARGET_VSX_TIMODE")]) + (define_mode_attr VI_char [(V2DI "d") (V4SI "w") (V8HI "h") (V16QI "b")]) (define_mode_attr VI_scalar [(V2DI "DI") (V4SI "SI") (V8HI "HI") (V16QI "QI")]) (define_mode_attr VI_unit [(V16QI "VECTOR_UNIT_ALTIVEC_P (V16QImode)") @@ -203,6 +214,9 @@ (define_mode_attr VP_small_lc [(V2DI "v4si") (V4SI "v8hi") (V8HI "v16qi")]) (define_mode_attr VU_char [(V2DI "w") (V4SI "h") (V8HI "b")]) +;; Vector negate +(define_mode_iterator VNEG [V4SI V2DI]) + ;; Vector move instructions. (define_insn "*altivec_mov" [(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*Y,*r,*r,v,v,*r") @@ -1949,32 +1963,30 @@ ;; Slightly prefer vperm, since the target does not overlap the source (define_insn "*altivec_vperm__internal" - [(set (match_operand:VM 0 "register_operand" "=v,?wo,?&wo") - (unspec:VM [(match_operand:VM 1 "register_operand" "v,0,wo") - (match_operand:VM 2 "register_operand" "v,wo,wo") - (match_operand:V16QI 3 "register_operand" "v,wo,wo")] + [(set (match_operand:VM 0 "register_operand" "=v,?wo") + (unspec:VM [(match_operand:VM 1 "register_operand" "v,0") + (match_operand:VM 2 "register_operand" "v,wo") + (match_operand:V16QI 3 "register_operand" "v,wo")] UNSPEC_VPERM))] "TARGET_ALTIVEC" "@ vperm %0,%1,%2,%3 - xxperm %x0,%x2,%x3 - xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3" + xxperm %x0,%x2,%x3" [(set_attr "type" "vecperm") - (set_attr "length" "4,4,8")]) + (set_attr "length" "4")]) (define_insn "altivec_vperm_v8hiv16qi" - [(set (match_operand:V16QI 0 "register_operand" "=v,?wo,?&wo") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v,0,wo") - (match_operand:V8HI 2 "register_operand" "v,wo,wo") - (match_operand:V16QI 3 "register_operand" "v,wo,wo")] + [(set (match_operand:V16QI 0 "register_operand" "=v,?wo") + (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v,0") + (match_operand:V8HI 2 "register_operand" "v,wo") + (match_operand:V16QI 3 "register_operand" "v,wo")] UNSPEC_VPERM))] "TARGET_ALTIVEC" "@ vperm %0,%1,%2,%3 - xxperm %x0,%x2,%x3 - xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3" + xxperm %x0,%x2,%x3" [(set_attr "type" "vecperm") - (set_attr "length" "4,4,8")]) + (set_attr "length" "4")]) (define_expand "altivec_vperm__uns" [(set (match_operand:VM 0 "register_operand" "") @@ -1992,18 +2004,17 @@ }) (define_insn "*altivec_vperm__uns_internal" - [(set (match_operand:VM 0 "register_operand" "=v,?wo,?&wo") - (unspec:VM [(match_operand:VM 1 "register_operand" "v,0,wo") - (match_operand:VM 2 "register_operand" "v,wo,wo") - (match_operand:V16QI 3 "register_operand" "v,wo,wo")] + [(set (match_operand:VM 0 "register_operand" "=v,?wo") + (unspec:VM [(match_operand:VM 1 "register_operand" "v,0") + (match_operand:VM 2 "register_operand" "v,wo") + (match_operand:V16QI 3 "register_operand" "v,wo")] UNSPEC_VPERM_UNS))] "TARGET_ALTIVEC" "@ vperm %0,%1,%2,%3 - xxperm %x0,%x2,%x3 - xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3" + xxperm %x0,%x2,%x3" [(set_attr "type" "vecperm") - (set_attr "length" "4,4,8")]) + (set_attr "length" "4")]) (define_expand "vec_permv16qi" [(set (match_operand:V16QI 0 "register_operand" "") @@ -2032,6 +2043,19 @@ FAIL; }) +(define_insn "*altivec_vpermr__internal" + [(set (match_operand:VM 0 "register_operand" "=v,?wo") + (unspec:VM [(match_operand:VM 1 "register_operand" "v,0") + (match_operand:VM 2 "register_operand" "v,wo") + (match_operand:V16QI 3 "register_operand" "v,wo")] + UNSPEC_VPERMR))] + "TARGET_P9_VECTOR" + "@ + vpermr %0,%1,%2,%3 + xxpermr %x0,%x2,%x3" + [(set_attr "type" "vecperm") + (set_attr "length" "4")]) + (define_insn "altivec_vrfip" ; ceil [(set (match_operand:V4SF 0 "register_operand" "=v") (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] @@ -2690,20 +2714,28 @@ DONE; }) +(define_insn "*p9_neg2" + [(set (match_operand:VNEG 0 "altivec_register_operand" "=v") + (neg:VNEG (match_operand:VNEG 1 "altivec_register_operand" "v")))] + "TARGET_P9_VECTOR" + "vneg %0,%1" + [(set_attr "type" "vecsimple")]) + (define_expand "neg2" - [(use (match_operand:VI 0 "register_operand" "")) - (use (match_operand:VI 1 "register_operand" ""))] - "TARGET_ALTIVEC" - " + [(set (match_operand:VI2 0 "register_operand" "") + (neg:VI2 (match_operand:VI2 1 "register_operand" "")))] + "" { - rtx vzero; + if (!TARGET_P9_VECTOR || (mode != V4SImode && mode != V2DImode)) + { + rtx vzero; - vzero = gen_reg_rtx (GET_MODE (operands[0])); - emit_insn (gen_altivec_vspltis (vzero, const0_rtx)); - emit_insn (gen_sub3 (operands[0], vzero, operands[1])); - - DONE; -}") + vzero = gen_reg_rtx (GET_MODE (operands[0])); + emit_move_insn (vzero, CONST0_RTX (mode)); + emit_insn (gen_sub3 (operands[0], vzero, operands[1])); + DONE; + } +}) (define_expand "udot_prod" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -2791,32 +2823,30 @@ "") (define_insn "vperm_v8hiv4si" - [(set (match_operand:V4SI 0 "register_operand" "=v,?wo,?&wo") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v,0,wo") - (match_operand:V4SI 2 "register_operand" "v,wo,wo") - (match_operand:V16QI 3 "register_operand" "v,wo,wo")] + [(set (match_operand:V4SI 0 "register_operand" "=v,?wo") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v,0") + (match_operand:V4SI 2 "register_operand" "v,wo") + (match_operand:V16QI 3 "register_operand" "v,wo")] UNSPEC_VPERMSI))] "TARGET_ALTIVEC" "@ vperm %0,%1,%2,%3 - xxperm %x0,%x2,%x3 - xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3" + xxperm %x0,%x2,%x3" [(set_attr "type" "vecperm") - (set_attr "length" "4,4,8")]) + (set_attr "length" "4")]) (define_insn "vperm_v16qiv8hi" - [(set (match_operand:V8HI 0 "register_operand" "=v,?wo,?&wo") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v,0,wo") - (match_operand:V8HI 2 "register_operand" "v,wo,wo") - (match_operand:V16QI 3 "register_operand" "v,wo,wo")] + [(set (match_operand:V8HI 0 "register_operand" "=v,?wo") + (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v,0") + (match_operand:V8HI 2 "register_operand" "v,wo") + (match_operand:V16QI 3 "register_operand" "v,wo")] UNSPEC_VPERMHI))] "TARGET_ALTIVEC" "@ vperm %0,%1,%2,%3 - xxperm %x0,%x2,%x3 - xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3" + xxperm %x0,%x2,%x3" [(set_attr "type" "vecperm") - (set_attr "length" "4,4,8")]) + (set_attr "length" "4")]) (define_expand "vec_unpacku_hi_v16qi" @@ -3353,7 +3383,7 @@ }") -;; Power8 vector instructions encoded as Altivec instructions +;; Power8/power9 vector instructions encoded as Altivec instructions ;; Vector count leading zeros (define_insn "*p8v_clz2" @@ -3364,6 +3394,15 @@ [(set_attr "length" "4") (set_attr "type" "vecsimple")]) +;; Vector count trailing zeros +(define_insn "*p9v_ctz2" + [(set (match_operand:VI2 0 "register_operand" "=v") + (ctz:VI2 (match_operand:VI2 1 "register_operand" "v")))] + "TARGET_P9_VECTOR" + "vctz %0,%1" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + ;; Vector population count (define_insn "*p8v_popcount2" [(set (match_operand:VI2 0 "register_operand" "=v") @@ -3373,6 +3412,15 @@ [(set_attr "length" "4") (set_attr "type" "vecsimple")]) +;; Vector parity +(define_insn "*p9v_parity2" + [(set (match_operand:VParity 0 "register_operand" "=v") + (parity:VParity (match_operand:VParity 1 "register_operand" "v")))] + "TARGET_P9_VECTOR" + "vprtyb %0,%1" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + ;; Vector Gather Bits by Bytes by Doubleword (define_insn "p8v_vgbbd" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -3540,6 +3588,27 @@ [(set_attr "length" "4") (set_attr "type" "vecsimple")]) +(define_insn "darn_32" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(const_int 0)] UNSPEC_DARN_32))] + "TARGET_MODULO" + "darn %0,0" + [(set_attr "type" "integer")]) + +(define_insn "darn_raw" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))] + "TARGET_MODULO && TARGET_64BIT" + "darn %0,2" + [(set_attr "type" "integer")]) + +(define_insn "darn" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(const_int 0)] UNSPEC_DARN))] + "TARGET_MODULO && TARGET_64BIT" + "darn %0,1" + [(set_attr "type" "integer")]) + (define_expand "bcd_" [(parallel [(set (reg:CCFP 74) (compare:CCFP diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index ea15764..ef8f617 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -140,6 +140,10 @@ (and (match_code "const_int") (match_test "TARGET_VSX && (ival == VECTOR_ELEMENT_SCALAR_64BIT)"))) +(define_constraint "wE" + "Vector constant that can be loaded with the XXSPLTIB instruction." + (match_test "xxspltib_constant_nosplit (op, mode)")) + ;; Extended fusion store (define_memory_constraint "wF" "Memory operand suitable for power9 fusion load/stores" @@ -156,11 +160,26 @@ (and (match_test "TARGET_DIRECT_MOVE_128") (match_test "(ival == VECTOR_ELEMENT_MFVSRLD_64BIT)")))) +;; Generate the XXORC instruction to set a register to all 1's +(define_constraint "wM" + "Match vector constant with all 1's if the XXLORC instruction is available" + (and (match_test "TARGET_P8_VECTOR") + (match_operand 0 "all_ones_constant"))) + +;; ISA 3.0 vector d-form addresses +(define_memory_constraint "wO" + "Memory operand suitable for the ISA 3.0 vector d-form instructions." + (match_operand 0 "vsx_quad_dform_memory_operand")) + ;; Lq/stq validates the address for load/store quad (define_memory_constraint "wQ" "Memory operand suitable for the load/store quad instructions" (match_operand 0 "quad_memory_operand")) +(define_constraint "wS" + "Vector constant that can be loaded with XXSPLTIB & sign extension." + (match_test "xxspltib_constant_split (op, mode)")) + ;; Altivec style load/store that ignores the bottom bits of the address (define_memory_constraint "wZ" "Indexed or indirect memory operand, ignoring the bottom 4 bits" diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 71fac76..d03d164 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -572,6 +572,38 @@ } }) +;; Return 1 if the operand is a CONST_VECTOR or VEC_DUPLICATE of a constant +;; that can loaded with a XXSPLTIB instruction and then a VUPKHSB, VECSB2W or +;; VECSB2D instruction. + +(define_predicate "xxspltib_constant_split" + (match_code "const_vector,vec_duplicate,const_int") +{ + int value = 256; + int num_insns = -1; + + if (!xxspltib_constant_p (op, mode, &num_insns, &value)) + return false; + + return num_insns > 1; +}) + + +;; Return 1 if the operand is a CONST_VECTOR that can loaded directly with a +;; XXSPLTIB instruction. + +(define_predicate "xxspltib_constant_nosplit" + (match_code "const_vector,vec_duplicate,const_int") +{ + int value = 256; + int num_insns = -1; + + if (!xxspltib_constant_p (op, mode, &num_insns, &value)) + return false; + + return num_insns == 1; +}) + ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a ;; vector register without using memory. (define_predicate "easy_vector_constant" @@ -590,7 +622,14 @@ if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)) { - if (zero_constant (op, mode)) + int value = 256; + int num_insns = -1; + + if (zero_constant (op, mode) || all_ones_constant (op, mode)) + return true; + + if (TARGET_P9_VECTOR + && xxspltib_constant_p (op, mode, &num_insns, &value)) return true; return easy_altivec_constant (op, mode); @@ -669,6 +708,11 @@ (and (match_code "const_int,const_double,const_wide_int,const_vector") (match_test "op == CONST0_RTX (mode)"))) +;; Return 1 if operand is constant -1 (scalars and vectors). +(define_predicate "all_ones_constant" + (and (match_code "const_int,const_double,const_wide_int,const_vector") + (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)"))) + ;; Return 1 if operand is 0.0. (define_predicate "zero_fp_constant" (and (match_code "const_double") @@ -698,48 +742,25 @@ (define_predicate "quad_memory_operand" (match_code "mem") { - rtx addr, op0, op1; - int ret; - if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI) - ret = 0; - - else if (!memory_operand (op, mode)) - ret = 0; - - else if (GET_MODE_SIZE (GET_MODE (op)) != 16) - ret = 0; - - else if (MEM_ALIGN (op) < 128) - ret = 0; - - else - { - addr = XEXP (op, 0); - if (int_reg_operand (addr, Pmode)) - ret = 1; + return false; - else if (GET_CODE (addr) != PLUS) - ret = 0; + if (GET_MODE_SIZE (mode) != 16 || !MEM_P (op) || MEM_ALIGN (op) < 128) + return false; - else - { - op0 = XEXP (addr, 0); - op1 = XEXP (addr, 1); - ret = (int_reg_operand (op0, Pmode) - && GET_CODE (op1) == CONST_INT - && IN_RANGE (INTVAL (op1), -32768, 32767) - && (INTVAL (op1) & 15) == 0); - } - } + return quad_address_p (XEXP (op, 0), mode, true); +}) - if (TARGET_DEBUG_ADDR) - { - fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false"); - debug_rtx (op); - } +;; Return 1 if the operand is suitable for load/store to vector registers with +;; d-form addressing (register+offset), which was added in ISA 3.0. +;; Unlike quad_memory_operand, we do not have to check for alignment. +(define_predicate "vsx_quad_dform_memory_operand" + (match_code "mem") +{ + if (!TARGET_P9_DFORM_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) != 16) + return false; - return ret; + return quad_address_p (XEXP (op, 0), mode, false); }) ;; Return 1 if the operand is an indexed or indirect memory operand. @@ -1054,6 +1075,10 @@ mode = V2DFmode; else if (mode == DImode) mode = V2DImode; + else if (mode == SImode && TARGET_P9_VECTOR) + mode = V4SImode; + else if (mode == SFmode && TARGET_P9_VECTOR) + mode = V4SFmode; else gcc_unreachable (); return memory_address_addr_space_p (mode, XEXP (op, 0), @@ -1091,10 +1116,6 @@ (define_special_predicate "equality_operator" (match_code "eq,ne")) -;; Return true if operand is MIN or MAX operator. -(define_predicate "min_max_operator" - (match_code "smin,smax,umin,umax")) - ;; Return 1 if OP is a comparison operation that is valid for a branch ;; instruction. We check the opcode against the mode of the CC value. ;; validate_condition_mode is an assertion. @@ -1137,6 +1158,11 @@ (and (match_operand 0 "branch_comparison_operator") (match_code "ne,le,ge,leu,geu,ordered"))) +;; Return 1 if OP is a comparison operator suitable for vector/scalar +;; comparisons that generate a -1/0 mask. +(define_predicate "fpmask_comparison_operator" + (match_code "eq,gt,ge")) + ;; Return 1 if OP is a comparison operation that is valid for a branch ;; insn, which is true if the corresponding bit in the CC register is set. (define_predicate "branch_positive_comparison_operator" diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 891d240..e0dac7c 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -24,6 +24,7 @@ . */ /* Before including this file, some macros must be defined: + RS6000_BUILTIN_0 -- 0 arg builtins RS6000_BUILTIN_1 -- 1 arg builtins RS6000_BUILTIN_2 -- 2 arg builtins RS6000_BUILTIN_3 -- 3 arg builtins @@ -43,6 +44,10 @@ ATTR builtin attribute information. ICODE Insn code of the function that implents the builtin. */ +#ifndef RS6000_BUILTIN_0 + #error "RS6000_BUILTIN_0 is not defined." +#endif + #ifndef RS6000_BUILTIN_1 #error "RS6000_BUILTIN_1 is not defined." #endif @@ -637,6 +642,41 @@ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ +/* Miscellaneous builtins for instructions added in ISA 3.0. These + instructions don't require either the DFP or VSX options, just the basic + ISA 3.0 enablement since they operate on general purpose registers. */ +#define BU_P9_MISC_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_MODULO, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +/* Miscellaneous builtins for instructions added in ISA 3.0. These + instructions don't require either the DFP or VSX options, just the basic + ISA 3.0 enablement since they operate on general purpose registers, + and they require 64-bit addressing. */ +#define BU_P9_64BIT_MISC_0(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_MODULO \ + | RS6000_BTM_64BIT, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_SPECIAL), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +/* Miscellaneous builtins for instructions added in ISA 3.0. These + instructions don't require either the DFP or VSX options, just the basic + ISA 3.0 enablement since they operate on general purpose registers. */ +#define BU_P9_MISC_0(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_MODULO, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_SPECIAL), \ + CODE_FOR_ ## ICODE) /* ICODE */ + /* 128-bit long double floating point builtins. */ #define BU_LDBL128_2(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ @@ -647,8 +687,113 @@ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ + +/* Miscellaneous builtins for instructions added in ISA 3.0. These + instructions don't require either the DFP or VSX options, just the basic + ISA 3.0 enablement since they operate on general purpose registers. */ +#define BU_P9_MISC_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_MODULO, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +/* Miscellaneous builtins for instructions added in ISA 3.0. These + instructions don't require either the DFP or VSX options, just the basic + ISA 3.0 enablement since they operate on general purpose registers, + and they require 64-bit addressing. */ +#define BU_P9_64BIT_MISC_0(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_MODULO \ + | RS6000_BTM_64BIT, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_SPECIAL), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +/* Miscellaneous builtins for instructions added in ISA 3.0. These + instructions don't require either the DFP or VSX options, just the basic + ISA 3.0 enablement since they operate on general purpose registers. */ +#define BU_P9_MISC_0(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_MODULO, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_SPECIAL), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +/* ISA 3.0 (power9) vector convenience macros. */ +/* For the instructions that are encoded as altivec instructions use + __builtin_altivec_ as the builtin name. */ +#define BU_P9V_AV_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_altivec_" NAME, /* NAME */ \ + RS6000_BTM_P9_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_P9V_AV_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_altivec_" NAME, /* NAME */ \ + RS6000_BTM_P9_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_P9V_AV_3(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_3 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_altivec_" NAME, /* NAME */ \ + RS6000_BTM_P9_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_P9V_AV_P(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_P (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_altivec_" NAME, /* NAME */ \ + RS6000_BTM_P9_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_PREDICATE), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +/* For the instructions encoded as VSX instructions use __builtin_vsx as the + builtin name. */ +#define BU_P9V_VSX_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_vsx_" NAME, /* NAME */ \ + RS6000_BTM_P9_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_P9V_OVERLOAD_1(ENUM, NAME) \ + RS6000_BUILTIN_1 (P9V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ + "__builtin_vec_" NAME, /* NAME */ \ + RS6000_BTM_P9_VECTOR, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_nothing) /* ICODE */ + +#define BU_P9V_OVERLOAD_2(ENUM, NAME) \ + RS6000_BUILTIN_2 (P9V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ + "__builtin_vec_" NAME, /* NAME */ \ + RS6000_BTM_P9_VECTOR, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_nothing) /* ICODE */ + +#define BU_P9V_OVERLOAD_3(ENUM, NAME) \ + RS6000_BUILTIN_3 (P9V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ + "__builtin_vec_" NAME, /* NAME */ \ + RS6000_BTM_P9_VECTOR, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_nothing) /* ICODE */ #endif + /* Insure 0 is not a legitimate index. */ BU_SPECIAL_X (RS6000_BUILTIN_NONE, NULL, 0, RS6000_BTC_MISC) @@ -1398,6 +1543,18 @@ BU_VSX_X (STXVW4X_V4SF, "stxvw4x_v4sf", MEM) BU_VSX_X (STXVW4X_V4SI, "stxvw4x_v4si", MEM) BU_VSX_X (STXVW4X_V8HI, "stxvw4x_v8hi", MEM) BU_VSX_X (STXVW4X_V16QI, "stxvw4x_v16qi", MEM) +BU_VSX_X (LD_ELEMREV_V2DF, "ld_elemrev_v2df", MEM) +BU_VSX_X (LD_ELEMREV_V2DI, "ld_elemrev_v2di", MEM) +BU_VSX_X (LD_ELEMREV_V4SF, "ld_elemrev_v4sf", MEM) +BU_VSX_X (LD_ELEMREV_V4SI, "ld_elemrev_v4si", MEM) +BU_VSX_X (LD_ELEMREV_V8HI, "ld_elemrev_v8hi", MEM) +BU_VSX_X (LD_ELEMREV_V16QI, "ld_elemrev_v16qi", MEM) +BU_VSX_X (ST_ELEMREV_V2DF, "st_elemrev_v2df", MEM) +BU_VSX_X (ST_ELEMREV_V2DI, "st_elemrev_v2di", MEM) +BU_VSX_X (ST_ELEMREV_V4SF, "st_elemrev_v4sf", MEM) +BU_VSX_X (ST_ELEMREV_V4SI, "st_elemrev_v4si", MEM) +BU_VSX_X (ST_ELEMREV_V8HI, "st_elemrev_v8hi", MEM) +BU_VSX_X (ST_ELEMREV_V16QI, "st_elemrev_v16qi", MEM) BU_VSX_X (XSABSDP, "xsabsdp", CONST) BU_VSX_X (XSADDDP, "xsadddp", FP) BU_VSX_X (XSCMPODP, "xscmpodp", FP) @@ -1455,6 +1612,8 @@ BU_VSX_OVERLOAD_1 (DOUBLE, "double") /* VSX builtins that are handled as special cases. */ BU_VSX_OVERLOAD_X (LD, "ld") BU_VSX_OVERLOAD_X (ST, "st") +BU_VSX_OVERLOAD_X (XL, "xl") +BU_VSX_OVERLOAD_X (XST, "xst") /* 1 argument VSX instructions added in ISA 2.07. */ BU_P8V_VSX_1 (XSCVSPDPN, "xscvspdpn", CONST, vsx_xscvspdpn) @@ -1639,12 +1798,37 @@ BU_P8V_MISC_3 (BCDSUB_OV, "bcdsub_ov", CONST, bcdsub_unordered) BU_DFP_MISC_2 (PACK_TD, "pack_dec128", CONST, packtd) BU_DFP_MISC_2 (UNPACK_TD, "unpack_dec128", CONST, unpacktd) +/* 0 argument general-purpose register functions added in ISA 3.0 (power9). */ +BU_P9_MISC_0 (DARN_32, "darn_32", MISC, darn_32) +BU_P9_64BIT_MISC_0 (DARN_RAW, "darn_raw", MISC, darn_raw) +BU_P9_64BIT_MISC_0 (DARN, "darn", MISC, darn) + BU_LDBL128_2 (PACK_TF, "pack_longdouble", CONST, packtf) BU_LDBL128_2 (UNPACK_TF, "unpack_longdouble", CONST, unpacktf) BU_P7_MISC_2 (PACK_V1TI, "pack_vector_int128", CONST, packv1ti) BU_P7_MISC_2 (UNPACK_V1TI, "unpack_vector_int128", CONST, unpackv1ti) +/* 1 argument vector functions added in ISA 3.0 (power9). */ +BU_P9V_AV_1 (VCTZB, "vctzb", CONST, ctzv16qi2) +BU_P9V_AV_1 (VCTZH, "vctzh", CONST, ctzv8hi2) +BU_P9V_AV_1 (VCTZW, "vctzw", CONST, ctzv4si2) +BU_P9V_AV_1 (VCTZD, "vctzd", CONST, ctzv2di2) +BU_P9V_AV_1 (VPRTYBD, "vprtybd", CONST, parityv2di2) +BU_P9V_AV_1 (VPRTYBQ, "vprtybq", CONST, parityv1ti2) +BU_P9V_AV_1 (VPRTYBW, "vprtybw", CONST, parityv4si2) + +/* ISA 3.0 vector overloaded 1 argument functions. */ +BU_P9V_OVERLOAD_1 (VCTZ, "vctz") +BU_P9V_OVERLOAD_1 (VCTZB, "vctzb") +BU_P9V_OVERLOAD_1 (VCTZH, "vctzh") +BU_P9V_OVERLOAD_1 (VCTZW, "vctzw") +BU_P9V_OVERLOAD_1 (VCTZD, "vctzd") +BU_P9V_OVERLOAD_1 (VPRTYB, "vprtyb") +BU_P9V_OVERLOAD_1 (VPRTYBD, "vprtybd") +BU_P9V_OVERLOAD_1 (VPRTYBQ, "vprtybq") +BU_P9V_OVERLOAD_1 (VPRTYBW, "vprtybw") + /* 1 argument crypto functions. */ BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox) diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index ceb80b2..5b4ccf1 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -2726,6 +2726,49 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, + ~RS6000_BTI_unsigned_V2DI, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, + ~RS6000_BTI_unsigned_long_long, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SF, + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SF, + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, + ~RS6000_BTI_unsigned_V16QI, 0 }, + { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, @@ -3475,6 +3518,55 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DF, + RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DF, + RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI, + RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI, + RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, + ~RS6000_BTI_long_long }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI, + RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, + ~RS6000_BTI_unsigned_V2DI }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI, + RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, + ~RS6000_BTI_unsigned_long_long }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SF, + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SF, + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI, + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI, + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI, + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, + ~RS6000_BTI_unsigned_V4SI }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI, + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, + ~RS6000_BTI_UINTSI }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI, + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI, + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI, + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, + ~RS6000_BTI_unsigned_V8HI }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI, + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, + ~RS6000_BTI_UINTHI }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI, + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI, + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI, + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, + ~RS6000_BTI_unsigned_V16QI }, + { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI, + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, + ~RS6000_BTI_UINTQI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, @@ -4123,6 +4215,43 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, + { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, + { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, + { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, + { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, + { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + + { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, + { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + + { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, + { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, + + { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, + + { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, + { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, @@ -4252,6 +4381,42 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, + { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, + { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 }, + { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, + { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, + RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 }, + { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, + RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 }, + + { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, + + { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, + { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + + { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 }, + { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, + { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, + RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 }, + { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, + RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 }, + { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 275404a..27239f1 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -60,13 +60,14 @@ | OPTION_MASK_UPPER_REGS_SF) /* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add - P9_DFORM or P9_MINMAX until they are fully debugged. */ + P9_MINMAX until the hardware that supports it is available. Do not add + P9_DFORM_VECTOR until LRA is the default register allocator. */ #define ISA_3_0_MASKS_SERVER (ISA_2_7_MASKS_SERVER \ | OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_ISEL \ | OPTION_MASK_MODULO \ | OPTION_MASK_P9_FUSION \ - | OPTION_MASK_P9_DFORM \ + | OPTION_MASK_P9_DFORM_SCALAR \ | OPTION_MASK_P9_VECTOR) #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) @@ -94,6 +95,7 @@ | OPTION_MASK_FPRND \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ + | OPTION_MASK_LRA \ | OPTION_MASK_MFCRF \ | OPTION_MASK_MFPGPR \ | OPTION_MASK_MODULO \ @@ -101,7 +103,8 @@ | OPTION_MASK_NO_UPDATE \ | OPTION_MASK_P8_FUSION \ | OPTION_MASK_P8_VECTOR \ - | OPTION_MASK_P9_DFORM \ + | OPTION_MASK_P9_DFORM_SCALAR \ + | OPTION_MASK_P9_DFORM_VECTOR \ | OPTION_MASK_P9_FUSION \ | OPTION_MASK_P9_MINMAX \ | OPTION_MASK_P9_VECTOR \ diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index d9a6b1f..6b4d178 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -31,6 +31,7 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int, #endif /* TREE_CODE */ extern bool easy_altivec_constant (rtx, machine_mode); +extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *); extern int vspltis_shifted (rtx); extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int); extern bool macho_lo_sum_memory_operand (rtx, machine_mode); @@ -86,6 +87,7 @@ extern int registers_ok_for_quad_peep (rtx, rtx); extern int mems_ok_for_quad_peep (rtx, rtx); extern bool gpr_or_gpr_p (rtx, rtx); extern bool direct_move_p (rtx, rtx); +extern bool quad_address_p (rtx, machine_mode, bool); extern bool quad_load_store_p (rtx, rtx); extern bool fusion_gpr_load_p (rtx, rtx, rtx, rtx); extern void expand_fusion_gpr_load (rtx *); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 1d0076c..7749483 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -452,6 +452,7 @@ typedef unsigned char addr_mask_type; #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */ #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */ #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */ +#define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */ /* Register type masks based on the type, of valid addressing modes. */ struct rs6000_reg_addr { @@ -499,6 +500,16 @@ mode_supports_vmx_dform (machine_mode mode) return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0); } +/* Return true if we have D-form addressing in VSX registers. This addressing + is more limited than normal d-form addressing in that the offset must be + aligned on a 16-byte boundary. */ +static inline bool +mode_supports_vsx_dform_quad (machine_mode mode) +{ + return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET) + != 0); +} + /* Target cpu costs. */ @@ -1128,6 +1139,7 @@ struct processor_costs ppca2_cost = { /* Table that classifies rs6000 builtin functions (pure, const, etc.). */ +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -1140,6 +1152,9 @@ struct processor_costs ppca2_cost = { #undef RS6000_BUILTIN_S #undef RS6000_BUILTIN_X +#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \ + { NAME, ICODE, MASK, ATTR }, + #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \ { NAME, ICODE, MASK, ATTR }, @@ -1185,6 +1200,7 @@ static const struct rs6000_builtin_info_type rs6000_builtin_info[] = #include "rs6000-builtin.def" }; +#undef RS6000_BUILTIN_0 #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 @@ -2105,7 +2121,9 @@ rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces) else if (keep_spaces) *p++ = ' '; - if ((mask & RELOAD_REG_OFFSET) != 0) + if ((mask & RELOAD_REG_QUAD_OFFSET) != 0) + *p++ = 'O'; + else if ((mask & RELOAD_REG_OFFSET) != 0) *p++ = 'o'; else if (keep_spaces) *p++ = ' '; @@ -2642,8 +2660,7 @@ rs6000_debug_reg_global (void) if (TARGET_LINK_STACK) fprintf (stderr, DEBUG_FMT_S, "link_stack", "true"); - if (targetm.lra_p ()) - fprintf (stderr, DEBUG_FMT_S, "lra", "true"); + fprintf (stderr, DEBUG_FMT_S, "lra", TARGET_LRA ? "true" : "false"); if (TARGET_P8_FUSION) { @@ -2769,17 +2786,31 @@ rs6000_setup_reg_addr_masks (void) } /* GPR and FPR registers can do REG+OFFSET addressing, except - possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form - addressing for scalars to altivec registers. */ + possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing + for 64-bit scalars and 32-bit SFmode to altivec registers. */ if ((addr_mask != 0) && !indexed_only_p && msize <= 8 && (rc == RELOAD_REG_GPR - || rc == RELOAD_REG_FPR - || (rc == RELOAD_REG_VMX - && TARGET_P9_DFORM - && (m2 == DFmode || m2 == SFmode)))) + || ((msize == 8 || m2 == SFmode) + && (rc == RELOAD_REG_FPR + || (rc == RELOAD_REG_VMX + && TARGET_P9_DFORM_SCALAR))))) addr_mask |= RELOAD_REG_OFFSET; + /* VSX registers can do REG+OFFSET addresssing if ISA 3.0 + instructions are enabled. The offset for 128-bit VSX registers is + only 12-bits. While GPRs can handle the full offset range, VSX + registers can only handle the restricted range. */ + else if ((addr_mask != 0) && !indexed_only_p + && msize == 16 && TARGET_P9_DFORM_VECTOR + && (ALTIVEC_OR_VSX_VECTOR_MODE (m2) + || (m2 == TImode && TARGET_VSX_TIMODE))) + { + addr_mask |= RELOAD_REG_OFFSET; + if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) + addr_mask |= RELOAD_REG_QUAD_OFFSET; + } + /* VMX registers can do (REG & -16) and ((REG+REG) & -16) addressing on 128-bit types. */ if (rc == RELOAD_REG_VMX && msize == 16 @@ -3102,7 +3133,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) } /* Support for new D-form instructions. */ - if (TARGET_P9_DFORM) + if (TARGET_P9_DFORM_SCALAR) rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS; /* Support for ISA 3.0 (power9) vectors. */ @@ -3621,6 +3652,9 @@ rs6000_builtin_mask_calculate (void) | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0) | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0) | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0) + | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0) + | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0) + | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0) | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0) | ((TARGET_HTM) ? RS6000_BTM_HTM : 0) | ((TARGET_DFP) ? RS6000_BTM_DFP : 0) @@ -3974,7 +4008,8 @@ rs6000_option_override_internal (bool global_init_p) /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno-