From: Jim Liu <jim.t90615@gmail.com>
Date: Tue, 24 May 2022 08:55:33 +0000 (+0800)
Subject: mmc: nuvoton: Add NPCM7xx mmc driver
X-Git-Tag: v2022.10~66^2~3
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3363a73ddfcda752256b8c06ffde75f6b8d5b819;p=platform%2Fkernel%2Fu-boot.git

mmc: nuvoton: Add NPCM7xx mmc driver

Add Nuvoton BMC NPCM750 mmc control driver.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
---

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 95d63b6..c5e1a1b 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -618,6 +618,18 @@ config MMC_SDHCI_MV
 
 	  If unsure, say N.
 
+config MMC_SDHCI_NPCM
+	bool "SDHCI support on Nuvoton NPCM device"
+	depends on MMC_SDHCI
+	depends on DM_MMC
+	help
+	  This selects the Secure Digital Host Controller Interface (SDHCI)
+	  on Nuvoton NPCM device.
+
+	  If you have a controller with this interface, say Y here.
+
+	  If unsure, say N.
+
 config MMC_SDHCI_PIC32
 	bool "Microchip PIC32 on-chip SDHCI support"
 	depends on DM_MMC && MACH_PIC32
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 7c42432..5d5104b 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_MMC_SDHCI_IPROC)		+= iproc_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_KONA)		+= kona_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_MSM)		+= msm_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_MV)		+= mv_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_NPCM)            += npcm_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_PIC32)		+= pic32_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_ROCKCHIP)	+= rockchip_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_S5P)		+= s5p_sdhci.o
diff --git a/drivers/mmc/npcm_sdhci.c b/drivers/mmc/npcm_sdhci.c
new file mode 100644
index 0000000..7eb17cc
--- /dev/null
+++ b/drivers/mmc/npcm_sdhci.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <sdhci.h>
+#include <clk.h>
+#include <power/regulator.h>
+
+#define NPCM_SDHC_MIN_FREQ	400000
+
+struct npcm_sdhci_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
+static int npcm_sdhci_probe(struct udevice *dev)
+{
+	struct npcm_sdhci_plat *plat = dev_get_plat(dev);
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+	struct sdhci_host *host = dev_get_priv(dev);
+	struct udevice *vqmmc_supply;
+	int vqmmc_uv, ret;
+	struct clk clk;
+
+	host->name = dev->name;
+	host->ioaddr = dev_read_addr_ptr(dev);
+	host->max_clk = dev_read_u32_default(dev, "clock-frequency", 0);
+
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (!ret && host->max_clk) {
+		ret = clk_set_rate(&clk, host->max_clk);
+		if (ret < 0)
+			return ret;
+	}
+
+	if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+		device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_supply);
+		vqmmc_uv = dev_read_u32_default(dev, "vqmmc-microvolt", 0);
+		/* Set IO voltage */
+		if (vqmmc_supply && vqmmc_uv)
+			regulator_set_value(vqmmc_supply, vqmmc_uv);
+	}
+
+	host->index = dev_read_u32_default(dev, "index", 0);
+	ret = mmc_of_parse(dev, &plat->cfg);
+	if (ret)
+		return ret;
+
+	host->mmc = &plat->mmc;
+	host->mmc->priv = host;
+	host->mmc->dev = dev;
+	upriv->mmc = host->mmc;
+
+	ret = sdhci_setup_cfg(&plat->cfg, host, 0, NPCM_SDHC_MIN_FREQ);
+	if (ret)
+		return ret;
+
+	return sdhci_probe(dev);
+}
+
+static int npcm_sdhci_bind(struct udevice *dev)
+{
+	struct npcm_sdhci_plat *plat = dev_get_plat(dev);
+
+	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id npcm_mmc_ids[] = {
+	{ .compatible = "nuvoton,npcm750-sdhci" },
+	{ .compatible = "nuvoton,npcm845-sdhci" },
+	{ }
+};
+
+U_BOOT_DRIVER(npcm_sdhci_drv) = {
+	.name           = "npcm_sdhci",
+	.id             = UCLASS_MMC,
+	.of_match       = npcm_mmc_ids,
+	.ops            = &sdhci_ops,
+	.bind           = npcm_sdhci_bind,
+	.probe          = npcm_sdhci_probe,
+	.priv_auto      = sizeof(struct sdhci_host),
+	.plat_auto      = sizeof(struct npcm_sdhci_plat),
+};