From: Andrew Waterman Date: Sun, 24 Sep 2017 01:04:16 +0000 (-0700) Subject: RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2 X-Git-Tag: users/ARM/embedded-binutils-master-2017q4~469 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3342be5dabeeaf2218dfbf4d38f92214612436f4;p=external%2Fbinutils.git RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2 This matches the ISA specification. This also adds two tests: one to make sure the assembler rejects invalid 'c.lui's, and one to make sure we only relax valid 'c.lui's. bfd/ChangeLog 2017-10-24 Andrew Waterman * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui when rd is x0. include/ChangeLog 2017-10-24 Andrew Waterman * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the immediate 0. gas/ChangeLog 2017-10-24 Andrew Waterman * testsuite/gas/riscv/c-lui-fail.d: New testcase. gas/testsuite/gas/riscv/c-lui-fail.l: Likewise. gas/testsuite/gas/riscv/c-lui-fail.s: Likewise. gas/testsuite/gas/riscv/riscv.exp: Likewise. ld/ChangeLog 2017-10-24 Andrew Waterman * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase. ld/testsuite/ld-riscv-elf/c-lui.s: Likewise. ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite. --- diff --git a/bfd/ChangeLog b/bfd/ChangeLog index a534b21..6f2f5e3 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,8 @@ +2017-10-24 Andrew Waterman + + * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui + when rd is x0. + 2017-10-24 Renlin Li PR ld/21703 diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c index f7cdb4e..b6e3892 100644 --- a/bfd/elfnn-riscv.c +++ b/bfd/elfnn-riscv.c @@ -2988,9 +2988,10 @@ _bfd_riscv_relax_lui (bfd *abfd, && VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval)) && VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval + ELF_MAXPAGESIZE))) { - /* Replace LUI with C.LUI if legal (i.e., rd != x2/sp). */ + /* Replace LUI with C.LUI if legal (i.e., rd != x0 and rd != x2/sp). */ bfd_vma lui = bfd_get_32 (abfd, contents + rel->r_offset); - if (((lui >> OP_SH_RD) & OP_MASK_RD) == X_SP) + unsigned rd = ((unsigned)lui >> OP_SH_RD) & OP_MASK_RD; + if (rd == 0 || rd == X_SP) return TRUE; lui = (lui & (OP_MASK_RD << OP_SH_RD)) | MATCH_C_LUI; diff --git a/gas/ChangeLog b/gas/ChangeLog index 7a9331d..a0f36f0 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2017-10-24 Andrew Waterman + + * testsuite/gas/riscv/c-lui-fail.d: New testcase. + gas/testsuite/gas/riscv/c-lui-fail.l: Likewise. + gas/testsuite/gas/riscv/c-lui-fail.s: Likewise. + gas/testsuite/gas/riscv/riscv.exp: Likewise. + 2017-10-24 H.J. Lu * config/tc-i386.c (md_pseudo_table): Add .code64 directive diff --git a/gas/testsuite/gas/riscv/c-lui-fail.d b/gas/testsuite/gas/riscv/c-lui-fail.d new file mode 100644 index 0000000..03e4596 --- /dev/null +++ b/gas/testsuite/gas/riscv/c-lui-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ic +#source: c-lui-fail.s +#error-output: c-lui-fail.l diff --git a/gas/testsuite/gas/riscv/c-lui-fail.l b/gas/testsuite/gas/riscv/c-lui-fail.l new file mode 100644 index 0000000..5a4e990 --- /dev/null +++ b/gas/testsuite/gas/riscv/c-lui-fail.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Error: illegal operands `c.lui x1,0' diff --git a/gas/testsuite/gas/riscv/c-lui-fail.s b/gas/testsuite/gas/riscv/c-lui-fail.s new file mode 100644 index 0000000..bb669bb --- /dev/null +++ b/gas/testsuite/gas/riscv/c-lui-fail.s @@ -0,0 +1,2 @@ +target: + c.lui x1, 0 diff --git a/gas/testsuite/gas/riscv/riscv.exp b/gas/testsuite/gas/riscv/riscv.exp index 005238f..f411335 100644 --- a/gas/testsuite/gas/riscv/riscv.exp +++ b/gas/testsuite/gas/riscv/riscv.exp @@ -21,4 +21,5 @@ if [istarget riscv*-*-*] { run_dump_test "t_insns" run_dump_test "fmv.x" + run_dump_test "c-lui-fail" } diff --git a/include/ChangeLog b/include/ChangeLog index c7e715b..dded883 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2017-10-24 Andrew Waterman + + * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the + immediate 0. + 2017-10-12 James Bowman * elf/ft32.h: Add R_FT32_15. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 719565d..015e781 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -141,7 +141,7 @@ static const char * const riscv_pred_succ[16] = #define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x)) #define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x)) #define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x)) -#define VALID_RVC_LUI_IMM(x) (EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x)) +#define VALID_RVC_LUI_IMM(x) (ENCODE_RVC_LUI_IMM(x) != 0 && EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x)) #define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x)) #define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x)) #define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x)) diff --git a/ld/ChangeLog b/ld/ChangeLog index 7319d72..f4c4490 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,9 @@ +2017-10-24 Andrew Waterman + + * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase. + ld/testsuite/ld-riscv-elf/c-lui.s: Likewise. + ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite. + 2017-10-24 Renlin Li PR ld/21703 diff --git a/ld/testsuite/ld-riscv-elf/c-lui.d b/ld/testsuite/ld-riscv-elf/c-lui.d new file mode 100644 index 0000000..7a96711 --- /dev/null +++ b/ld/testsuite/ld-riscv-elf/c-lui.d @@ -0,0 +1,17 @@ +#name: lui to c.lui relaxation +#source: c-lui.s +#as: -march=rv32ic +#ld: -shared -melf32lriscv +#objdump: -d -M no-aliases,numeric + +.*: file format .* + + +Disassembly of section \.text: + +.* <.text>: +.*: 6085 c.lui x1,0x1 +.*: 000000b7 lui x1,0x0 +.*: 00001037 lui x0,0x1 +.*: 00001137 lui x2,0x1 +#pass diff --git a/ld/testsuite/ld-riscv-elf/c-lui.s b/ld/testsuite/ld-riscv-elf/c-lui.s new file mode 100644 index 0000000..4a23fdb --- /dev/null +++ b/ld/testsuite/ld-riscv-elf/c-lui.s @@ -0,0 +1,5 @@ +.text + lui x1, 1 + lui x1, 0 + lui x0, 1 + lui x2, 1 diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp new file mode 100644 index 0000000..efe012e --- /dev/null +++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp @@ -0,0 +1,24 @@ +# Expect script for RISC-V ELF linker tests +# Copyright (C) 2017 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. +# + +if [is_target "riscv-*-*"] { + run_dump_test "c-lui" +}