From: jgreenhalgh Date: Wed, 1 May 2013 10:46:00 +0000 (+0000) Subject: [AArch64] Add combiner patterns for FAC instructions X-Git-Tag: upstream/4.9.2~6289 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3310ab7fcdefa43029412ba17817192626b5e4df;p=platform%2Fupstream%2Flinaro-gcc.git [AArch64] Add combiner patterns for FAC instructions gcc/ * config/aarch64/aarch64-simd.md (*aarch64_fac): New. * config/aarch64/iterators.md (FAC_COMPARISONS): New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@198494 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d0392c8..ccc1fc7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2013-05-01 James Greenhalgh + * config/aarch64/aarch64-simd.md (*aarch64_fac): New. + * config/aarch64/iterators.md (FAC_COMPARISONS): New. + +2013-05-01 James Greenhalgh + * config/aarch64/aarch64-simd.md (vcond_internal): Handle special cases for constant masks. (vcond): Allow nonmemory_operands for outcome vectors. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index dfe4acb..21c2a68 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3400,6 +3400,23 @@ (set_attr "simd_mode" "")] ) +;; fac(ge|gt) +;; Note we can also handle what would be fac(le|lt) by +;; generating fac(ge|gt). + +(define_insn "*aarch64_fac" + [(set (match_operand: 0 "register_operand" "=w") + (neg: + (FAC_COMPARISONS: + (abs:VALLF (match_operand:VALLF 1 "register_operand" "w")) + (abs:VALLF (match_operand:VALLF 2 "register_operand" "w")) + )))] + "TARGET_SIMD" + "fac\t%0, %, %" + [(set_attr "simd_type" "simd_fcmp") + (set_attr "simd_mode" "")] +) + ;; addp (define_insn "aarch64_addp" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 0b9f9e8..00e315d 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -553,6 +553,9 @@ ;; Unsigned comparison operators. (define_code_iterator UCOMPARISONS [ltu leu geu gtu]) +;; Unsigned comparison operators. +(define_code_iterator FAC_COMPARISONS [lt le ge gt]) + ;; ------------------------------------------------------------------- ;; Code Attributes ;; -------------------------------------------------------------------