From: Tom Musta Date: Wed, 12 Feb 2014 21:22:52 +0000 (-0600) Subject: target-ppc: Altivec 2.07: Add Instruction Flag X-Git-Tag: TizenStudio_2.0_p2.3.2~208^2~1017^2~39 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=32ea54ab5fe18954e05f33a5825ba088d6cd4163;p=sdk%2Femulator%2Fqemu.git target-ppc: Altivec 2.07: Add Instruction Flag This patch adds a flag that will be used to tag the Altivec instructions introduced in Power ISA Version 2.07. The flag is added to Power8 model since P8 supports these instructions. Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 7cf7255..88c2788 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1893,12 +1893,15 @@ enum { PPC2_BCTAR_ISA207 = 0x0000000000001000ULL, /* ISA 2.07 load/store quadword */ PPC2_LSQ_ISA207 = 0x0000000000002000ULL, + /* ISA 2.07 Altivec */ + PPC2_ALTIVEC_207 = 0x0000000000004000ULL, #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ - PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207) + PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ + PPC2_ALTIVEC_207) }; /*****************************************************************************/ diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index b9576ac..9dd8c1c 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7172,7 +7172,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | - PPC2_LSQ_ISA207; + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207; pcc->msr_mask = 0x800000000284FF36ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU)