From: Richard Sandiford Date: Tue, 18 Jun 2019 14:47:42 +0000 (+0000) Subject: [AArch64] Simplify SVE IFN_COND patterns X-Git-Tag: upstream/12.2.0~23865 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=32cf949cec180799d3fb14d405772ea35b5aafd3;p=platform%2Fupstream%2Fgcc.git [AArch64] Simplify SVE IFN_COND patterns This patch makes the binary IFN_COND patterns use the same approach as the ternary patterns, with one pattern handling the cases in which the "else" value isn't tied to one of the other inputs. 2019-06-18 Richard Sandiford Kugan Vivekanandarajah gcc/ * config/aarch64/aarch64-sve.md (*cond__0): Delete. (*cond__z): Fold into... (*cond__any): ...here. Also handle cases in which operand 4 can be tied to operand 0 (either inherently or via RA). From-SVN: r272423 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 461792c..19ab09e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-06-18 Richard Sandiford + + * config/aarch64/aarch64-sve.md (*cond__0): Delete. + (*cond__z): Fold into... + (*cond__any): ...here. Also handle cases in which + operand 4 can be tied to operand 0 (either inherently or via RA). + 2019-06-18 Richard Biener PR debug/90900 diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 806823f..ed895a8 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -1868,41 +1868,6 @@ "TARGET_SVE" ) -;; Predicated integer operations with select matching the output operand. -(define_insn "*cond__0" - [(set (match_operand:SVE_I 0 "register_operand" "+w, w, ?&w") - (unspec:SVE_I - [(match_operand: 1 "register_operand" "Upl, Upl, Upl") - (SVE_INT_BINARY:SVE_I - (match_operand:SVE_I 2 "register_operand" "0, w, w") - (match_operand:SVE_I 3 "register_operand" "w, 0, w")) - (match_dup 0)] - UNSPEC_SEL))] - "TARGET_SVE" - "@ - \t%0., %1/m, %0., %3. - \t%0., %1/m, %0., %2. - movprfx\t%0, %1/m, %2\;\t%0., %1/m, %0., %3." - [(set_attr "movprfx" "*,*,yes")] -) - -(define_insn "*cond__0" - [(set (match_operand:SVE_SDI 0 "register_operand" "+w, w, ?&w") - (unspec:SVE_SDI - [(match_operand: 1 "register_operand" "Upl, Upl, Upl") - (SVE_INT_BINARY_SD:SVE_SDI - (match_operand:SVE_SDI 2 "register_operand" "0, w, w") - (match_operand:SVE_SDI 3 "register_operand" "w, 0, w")) - (match_dup 0)] - UNSPEC_SEL))] - "TARGET_SVE" - "@ - \t%0., %1/m, %0., %3. - \t%0., %1/m, %0., %2. - movprfx\t%0, %1/m, %2\;\t%0., %1/m, %0., %3." - [(set_attr "movprfx" "*,*,yes")] -) - ;; Predicated integer operations with select matching the first operand. (define_insn "*cond__2" [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") @@ -1969,78 +1934,64 @@ [(set_attr "movprfx" "*,yes")] ) -;; Predicated integer operations with select matching zero. -(define_insn "*cond__z" - [(set (match_operand:SVE_I 0 "register_operand" "=&w") - (unspec:SVE_I - [(match_operand: 1 "register_operand" "Upl") - (SVE_INT_BINARY:SVE_I - (match_operand:SVE_I 2 "register_operand" "w") - (match_operand:SVE_I 3 "register_operand" "w")) - (match_operand:SVE_I 4 "aarch64_simd_imm_zero")] - UNSPEC_SEL))] - "TARGET_SVE" - "movprfx\t%0., %1/z, %2.\;\t%0., %1/m, %0., %3." - [(set_attr "movprfx" "yes")] -) - -(define_insn "*cond__z" - [(set (match_operand:SVE_SDI 0 "register_operand" "=&w") - (unspec:SVE_SDI - [(match_operand: 1 "register_operand" "Upl") - (SVE_INT_BINARY_SD:SVE_SDI - (match_operand:SVE_SDI 2 "register_operand" "w") - (match_operand:SVE_SDI 3 "register_operand" "w")) - (match_operand:SVE_SDI 4 "aarch64_simd_imm_zero")] - UNSPEC_SEL))] - "TARGET_SVE" - "movprfx\t%0., %1/z, %2.\;\t%0., %1/m, %0., %3." - [(set_attr "movprfx" "yes")] -) - -;; Synthetic predications with select unmatched. +;; Predicated integer binary operations in which the values of inactive +;; lanes are distinct from the other inputs. (define_insn_and_rewrite "*cond__any" - [(set (match_operand:SVE_I 0 "register_operand" "=&w") + [(set (match_operand:SVE_I 0 "register_operand" "=&w, &w, &w, &w, ?&w") (unspec:SVE_I - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl, Upl, Upl, Upl") (SVE_INT_BINARY:SVE_I - (match_operand:SVE_I 2 "register_operand" "w") - (match_operand:SVE_I 3 "register_operand" "w")) - (match_operand:SVE_I 4 "register_operand" "w")] + (match_operand:SVE_I 2 "register_operand" "0, w, w, w, w") + (match_operand:SVE_I 3 "register_operand" "w, 0, w, w, w")) + (match_operand:SVE_I 4 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, 0, w")] UNSPEC_SEL))] "TARGET_SVE - && !(rtx_equal_p (operands[0], operands[4]) - || rtx_equal_p (operands[2], operands[4]) - || rtx_equal_p (operands[3], operands[4]))" - "#" - "&& reload_completed" + && !rtx_equal_p (operands[2], operands[4]) + && !rtx_equal_p (operands[3], operands[4])" + "@ + movprfx\t%0., %1/z, %0.\;\t%0., %1/m, %0., %3. + movprfx\t%0., %1/z, %0.\;\t%0., %1/m, %0., %2. + movprfx\t%0., %1/z, %2.\;\t%0., %1/m, %0., %3. + movprfx\t%0., %1/m, %2.\;\t%0., %1/m, %0., %3. + #" + "&& reload_completed + && register_operand (operands[4], mode) + && !rtx_equal_p (operands[0], operands[4])" { emit_insn (gen_vcond_mask_ (operands[0], operands[2], operands[4], operands[1])); operands[4] = operands[2] = operands[0]; } + [(set_attr "movprfx" "yes")] ) (define_insn_and_rewrite "*cond__any" - [(set (match_operand:SVE_SDI 0 "register_operand" "=&w") + [(set (match_operand:SVE_SDI 0 "register_operand" "=&w, &w, &w, &w, ?&w") (unspec:SVE_SDI - [(match_operand: 1 "register_operand" "Upl") - (SVE_INT_BINARY_SD:SVE_I - (match_operand:SVE_SDI 2 "register_operand" "w") - (match_operand:SVE_SDI 3 "register_operand" "w")) - (match_operand:SVE_SDI 4 "register_operand" "w")] + [(match_operand: 1 "register_operand" "Upl, Upl, Upl, Upl, Upl") + (SVE_INT_BINARY_SD:SVE_SDI + (match_operand:SVE_SDI 2 "register_operand" "0, w, w, w, w") + (match_operand:SVE_SDI 3 "register_operand" "w, 0, w, w, w")) + (match_operand:SVE_SDI 4 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, 0, w")] UNSPEC_SEL))] "TARGET_SVE - && !(rtx_equal_p (operands[0], operands[4]) - || rtx_equal_p (operands[2], operands[4]) - || rtx_equal_p (operands[3], operands[4]))" - "#" - "&& reload_completed" + && !rtx_equal_p (operands[2], operands[4]) + && !rtx_equal_p (operands[3], operands[4])" + "@ + movprfx\t%0., %1/z, %0.\;\t%0., %1/m, %0., %3. + movprfx\t%0., %1/z, %0.\;\t%0., %1/m, %0., %2. + movprfx\t%0., %1/z, %2.\;\t%0., %1/m, %0., %3. + movprfx\t%0., %1/m, %2.\;\t%0., %1/m, %0., %3. + #" + "&& reload_completed + && register_operand (operands[4], mode) + && !rtx_equal_p (operands[0], operands[4])" { emit_insn (gen_vcond_mask_ (operands[0], operands[2], operands[4], operands[1])); operands[4] = operands[2] = operands[0]; } + [(set_attr "movprfx" "yes")] ) ;; Set operand 0 to the last active element in operand 3, or to tied @@ -2874,25 +2825,6 @@ "TARGET_SVE" ) -;; Predicated floating-point operations with select matching output. -(define_insn "*cond__0" - [(set (match_operand:SVE_F 0 "register_operand" "+w, w, ?&w") - (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl, Upl") - (unspec:SVE_F - [(match_operand:SVE_F 2 "register_operand" "0, w, w") - (match_operand:SVE_F 3 "register_operand" "w, 0, w")] - SVE_COND_FP_BINARY) - (match_dup 0)] - UNSPEC_SEL))] - "TARGET_SVE" - "@ - \t%0., %1/m, %0., %3. - \t%0., %1/m, %0., %2. - movprfx\t%0, %1/m, %2\;\t%0., %1/m, %0., %3." - [(set_attr "movprfx" "*,*,yes")] -) - ;; Predicated floating-point operations with select matching first operand. (define_insn "*cond__2" [(set (match_operand:SVE_F 0 "register_operand" "=w, ?&w") @@ -2929,45 +2861,36 @@ [(set_attr "movprfx" "*,yes")] ) -;; Predicated floating-point operations with select matching zero. -(define_insn "*cond__z" - [(set (match_operand:SVE_F 0 "register_operand" "=&w") - (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl") - (unspec:SVE_F - [(match_operand:SVE_F 2 "register_operand" "w") - (match_operand:SVE_F 3 "register_operand" "w")] - SVE_COND_FP_BINARY) - (match_operand:SVE_F 4 "aarch64_simd_imm_zero")] - UNSPEC_SEL))] - "TARGET_SVE" - "movprfx\t%0., %1/z, %2.\;\t%0., %1/m, %0., %3." - [(set_attr "movprfx" "yes")] -) - -;; Synthetic predication of floating-point operations with select unmatched. +;; Predicated floating-point binary operations in which the values of +;; inactive lanes are distinct from the other inputs. (define_insn_and_rewrite "*cond__any" - [(set (match_operand:SVE_F 0 "register_operand" "=&w") + [(set (match_operand:SVE_F 0 "register_operand" "=&w, &w, &w, &w, ?&w") (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl, Upl, Upl, Upl") (unspec:SVE_F - [(match_operand:SVE_F 2 "register_operand" "w") - (match_operand:SVE_F 3 "register_operand" "w")] + [(match_operand:SVE_F 2 "register_operand" "0, w, w, w, w") + (match_operand:SVE_F 3 "register_operand" "w, 0, w, w, w")] SVE_COND_FP_BINARY) - (match_operand:SVE_F 4 "register_operand" "w")] + (match_operand:SVE_F 4 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, 0, w")] UNSPEC_SEL))] - "TARGET_SVE" - "#" + "TARGET_SVE + && !rtx_equal_p (operands[2], operands[4]) + && !rtx_equal_p (operands[3], operands[4])" + "@ + movprfx\t%0., %1/z, %0.\;\t%0., %1/m, %0., %3. + movprfx\t%0., %1/z, %0.\;\t%0., %1/m, %0., %2. + movprfx\t%0., %1/z, %2.\;\t%0., %1/m, %0., %3. + movprfx\t%0., %1/m, %2.\;\t%0., %1/m, %0., %3. + #" "&& reload_completed - && !(rtx_equal_p (operands[0], operands[4]) - || rtx_equal_p (operands[2], operands[4]) - || rtx_equal_p (operands[3], operands[4]))" - ; Not matchable by any one insn or movprfx insn. We need a separate select. + && register_operand (operands[4], mode) + && !rtx_equal_p (operands[0], operands[4])" { emit_insn (gen_vcond_mask_ (operands[0], operands[2], operands[4], operands[1])); operands[4] = operands[2] = operands[0]; } + [(set_attr "movprfx" "yes")] ) ;; Predicated floating-point ternary operations with select.