From: Zhigang Gong <zhigang.gong@intel.com>
Date: Wed, 22 Jan 2014 02:32:08 +0000 (+0800)
Subject: GBE: increase the disassembly output's readability.
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3262ebecac132b0adf168e8f5efc2f6993a1fe92;p=contrib%2Fbeignet.git

GBE: increase the disassembly output's readability.

Add label information and the instruction address
prefix. Make the address consistent with fulsim.
And also make the register allocation output a little
bit prettier.

Now the disassembly output is as below:
compiler_ceil's disassemble begin:
  L0:
    (0       )  mov(1)          f0<1>UW         0x0UW                           { align1 WE_all };
    ....
    (32      )  (+f0) mov(16)   g1<1>UW         0x1UW                           { align1 WE_normal 1H };
  L1:
    (34      )  mov(16)         g112<1>UD       g0<8,8,1>UD                     { align1 WE_all 1H };
    ...
compiler_ceil's disassemble end.

The register allocation output is as below:
%26      g2  .8   4  B  [0        -> 0       ]
%28      g2  .12  4  B  [0        -> 6       ]
%29      g2  .16  4  B  [0        -> 9       ]
%30      g126.0   64 B  [2        -> 3       ]
%31      g124.0   64 B  [3        -> 4       ]

Please be noted, the register allocation's output is not correct
when the register is a pure scalar(bool) register which allocated
at the backend instruction selection stage. To be fixed.

Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: Yang Rong <rong.r.yang@intel.com>
---

diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index ecb8ef3..584d9d0 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -33,6 +33,8 @@
 #include "ir/function.hpp"
 #include "sys/cvar.hpp"
 #include <cstring>
+#include <iostream>
+#include <iomanip>
 
 namespace gbe
 {
@@ -1878,9 +1880,20 @@ namespace gbe
     genKernel->insnNum = p->store.size();
     genKernel->insns = GBE_NEW_ARRAY_NO_ARG(GenInstruction, genKernel->insnNum);
     std::memcpy(genKernel->insns, &p->store[0], genKernel->insnNum * sizeof(GenInstruction));
-    if (OCL_OUTPUT_ASM)
-      for (uint32_t insnID = 0; insnID < genKernel->insnNum; ++insnID)
+    if (OCL_OUTPUT_ASM) {
+      std::cout << genKernel->getName() << "'s disassemble begin:" << std::endl;
+      ir::LabelIndex curLabel = (ir::LabelIndex)0;
+      std::cout << "  L0:" << std::endl;
+      for (uint32_t insnID = 0; insnID < genKernel->insnNum; ++insnID) {
+        if (labelPos.find((ir::LabelIndex)(curLabel + 1))->second == insnID) {
+          std::cout << "  L" << curLabel + 1 << ":" << std::endl;
+          curLabel = (ir::LabelIndex)(curLabel + 1);
+        }
+        std::cout << "    (" << std::setw(8) << insnID * 2 << ")  ";
         gen_disasm(stdout, &p->store[insnID]);
+      }
+      std::cout << genKernel->getName() << "'s disassemble end." << std::endl;
+    }
     return true;
   }
 
diff --git a/backend/src/backend/gen_reg_allocation.cpp b/backend/src/backend/gen_reg_allocation.cpp
index 25db169..51a9f76 100644
--- a/backend/src/backend/gen_reg_allocation.cpp
+++ b/backend/src/backend/gen_reg_allocation.cpp
@@ -691,9 +691,11 @@ namespace gbe
           if (!ctx.isScalarReg(vReg))
             registerSize *= ctx.getSimdWidth();
         }
-        cout << "%" << setw(-8) << vReg << "\tg" << setw(-3) << reg << "." << setw(-2) << subreg << "B"
-             <<  "\t" << setw(3) << registerSize
-             << "\t[" << setw(8) << this->intervals[(uint)vReg].minID
+        cout << "%" << setiosflags(ios::left) << setw(8) << vReg << "g"
+             << setiosflags(ios::left) << setw(3) << reg << "."
+             << setiosflags(ios::left) << setw(2) << subreg
+             <<  "  " << setw(3) << registerSize << "B"
+             << "  [" << setw(8) << this->intervals[(uint)vReg].minID
              << " -> " << setw(8) << this->intervals[(uint)vReg].maxID
              << "]" << endl;
     }