From: Simon Pilgrim Date: Sun, 21 Nov 2021 12:01:44 +0000 (+0000) Subject: [ARM][ParallelDSP] Regenerate complex_dot_prod.ll test X-Git-Tag: upstream/15.0.7~25141 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3234f2d9c1669459833e717d34c10296d78b7818;p=platform%2Fupstream%2Fllvm.git [ARM][ParallelDSP] Regenerate complex_dot_prod.ll test --- diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/complex_dot_prod.ll b/llvm/test/CodeGen/ARM/ParallelDSP/complex_dot_prod.ll index fab5aba..76bd80c 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/complex_dot_prod.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/complex_dot_prod.ll @@ -1,52 +1,150 @@ -; RUN: llc -mtriple=thumbv7em -mcpu=cortex-m4 -O3 %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LLC -; RUN: opt -S -mtriple=armv7-a -arm-parallel-dsp -dce %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-OPT - -; TODO: Think we should be able to use smlsdx/smlsldx here. - -; CHECK-LABEL: complex_dot_prod - -; CHECK-LLC: smlaldx -; CHECK-LLC: smulbb -; CHECK-LLC: smultt -; CHECK-LLC: smlaldx -; CHECK-LLC: smlalbb -; CHECK-LLC: smultt -; CHECK-LLC: smlalbb -; CHECK-LLC: smultt -; CHECK-LLC: smlaldx -; CHECK-LLC: smlalbb -; CHECK-LLC: smultt -; CHECK-LLC: smlaldx -; CHECK-LCC: pop.w {r4, r5, r6, r7, r8, r9, r10, pc} - -; CHECK-OPT: [[ADDR_A:%[^ ]+]] = bitcast i16* %pSrcA to i32* -; CHECK-OPT: [[A:%[^ ]+]] = load i32, i32* [[ADDR_A]], align 2 -; CHECK-OPT: [[ADDR_A_2:%[^ ]+]] = getelementptr inbounds i16, i16* %pSrcA, i32 2 -; CHECK-OPT: [[ADDR_B:%[^ ]+]] = bitcast i16* %pSrcB to i32* -; CHECK-OPT: [[B:%[^ ]+]] = load i32, i32* [[ADDR_B]], align 2 -; CHECK-OPT: [[ACC0:%[^ ]+]] = call i64 @llvm.arm.smlaldx(i32 [[A]], i32 [[B]], i64 0) -; CHECK-OPT: [[ADDR_B_2:%[^ ]+]] = getelementptr inbounds i16, i16* %pSrcB, i32 2 -; CHECK-OPT: [[CAST_ADDR_A_2:%[^ ]+]] = bitcast i16* [[ADDR_A_2]] to i32* -; CHECK-OPT: [[A_2:%[^ ]+]] = load i32, i32* [[CAST_ADDR_A_2]], align 2 -; CHECK-OPT: [[ADDR_A_4:%[^ ]+]] = getelementptr inbounds i16, i16* %pSrcA, i32 4 -; CHECK-OPT: [[CAST_ADDR_B_2:%[^ ]+]] = bitcast i16* [[ADDR_B_2]] to i32* -; CHECK-OPT: [[B_2:%[^ ]+]] = load i32, i32* [[CAST_ADDR_B_2]], align 2 -; CHECK-OPT: [[ACC1:%[^ ]+]] = call i64 @llvm.arm.smlaldx(i32 [[A_2]], i32 [[B_2]], i64 [[ACC0]]) -; CHECK-OPT: [[ADDR_B_4:%[^ ]+]] = getelementptr inbounds i16, i16* %pSrcB, i32 4 -; CHECK-OPT: [[CAST_ADDR_A_4:%[^ ]+]] = bitcast i16* [[ADDR_A_4]] to i32* -; CHECK-OPT: [[A_4:%[^ ]+]] = load i32, i32* [[CAST_ADDR_A_4]], align 2 -; CHECK-OPT: [[ADDR_A_6:%[^ ]+]] = getelementptr inbounds i16, i16* %pSrcA, i32 6 -; CHECK-OPT: [[CAST_ADDR_B_4:%[^ ]+]] = bitcast i16* [[ADDR_B_4]] to i32* -; CHECK-OPT: [[B_4:%[^ ]+]] = load i32, i32* [[CAST_ADDR_B_4]], align 2 -; CHECK-OPT: [[ACC2:%[^ ]+]] = call i64 @llvm.arm.smlaldx(i32 [[A_4]], i32 [[B_4]], i64 [[ACC1]]) -; CHECK-OPT: [[ADDR_B_6:%[^ ]+]] = getelementptr inbounds i16, i16* %pSrcB, i32 6 -; CHECK-OPT: [[CAST_ADDR_A_6:%[^ ]+]] = bitcast i16* [[ADDR_A_6]] to i32* -; CHECK-OPT: [[A_6:%[^ ]+]] = load i32, i32* [[CAST_ADDR_A_6]], align 2 -; CHECK-OPT: [[CAST_ADDR_B_6:%[^ ]+]] = bitcast i16* [[ADDR_B_6]] to i32* -; CHECK-OPT: [[B_6:%[^ ]+]] = load i32, i32* [[CAST_ADDR_B_6]], align 2 -; CHECK-OPT: call i64 @llvm.arm.smlaldx(i32 [[A_6]], i32 [[B_6]], i64 [[ACC2]]) +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=thumbv7em -mcpu=cortex-m4 -O3 %s -o - | FileCheck %s --check-prefix=CHECK-LLC +; RUN: opt -S -mtriple=armv7-a -arm-parallel-dsp -dce %s -o - | FileCheck %s --check-prefix=CHECK-OPT define dso_local arm_aapcscc void @complex_dot_prod(i16* nocapture readonly %pSrcA, i16* nocapture readonly %pSrcB, i32* nocapture %realResult, i32* nocapture %imagResult) { +; CHECK-LLC-LABEL: complex_dot_prod: +; CHECK-LLC: @ %bb.0: @ %entry +; CHECK-LLC-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; CHECK-LLC-NEXT: ldr r5, [r0] +; CHECK-LLC-NEXT: ldr r7, [r1] +; CHECK-LLC-NEXT: ldr.w r10, [r0, #4] +; CHECK-LLC-NEXT: ldr.w r8, [r0, #8] +; CHECK-LLC-NEXT: ldr.w r12, [r0, #12] +; CHECK-LLC-NEXT: ldr r4, [r1, #4] +; CHECK-LLC-NEXT: ldr.w r9, [r1, #8] +; CHECK-LLC-NEXT: ldr.w lr, [r1, #12] +; CHECK-LLC-NEXT: movs r0, #0 +; CHECK-LLC-NEXT: movs r1, #0 +; CHECK-LLC-NEXT: smlaldx r0, r1, r5, r7 +; CHECK-LLC-NEXT: smulbb r6, r7, r5 +; CHECK-LLC-NEXT: smultt r5, r7, r5 +; CHECK-LLC-NEXT: asr.w r11, r6, #31 +; CHECK-LLC-NEXT: subs r6, r6, r5 +; CHECK-LLC-NEXT: sbc.w r5, r11, r5, asr #31 +; CHECK-LLC-NEXT: smlaldx r0, r1, r10, r4 +; CHECK-LLC-NEXT: smlalbb r6, r5, r4, r10 +; CHECK-LLC-NEXT: smultt r4, r4, r10 +; CHECK-LLC-NEXT: subs r6, r6, r4 +; CHECK-LLC-NEXT: sbc.w r4, r5, r4, asr #31 +; CHECK-LLC-NEXT: smlalbb r6, r4, r9, r8 +; CHECK-LLC-NEXT: smultt r5, r9, r8 +; CHECK-LLC-NEXT: subs r6, r6, r5 +; CHECK-LLC-NEXT: sbc.w r4, r4, r5, asr #31 +; CHECK-LLC-NEXT: smlaldx r0, r1, r8, r9 +; CHECK-LLC-NEXT: smlalbb r6, r4, lr, r12 +; CHECK-LLC-NEXT: smultt r7, lr, r12 +; CHECK-LLC-NEXT: smlaldx r0, r1, r12, lr +; CHECK-LLC-NEXT: subs r6, r6, r7 +; CHECK-LLC-NEXT: sbc.w r7, r4, r7, asr #31 +; CHECK-LLC-NEXT: lsrs r6, r6, #6 +; CHECK-LLC-NEXT: lsrs r0, r0, #6 +; CHECK-LLC-NEXT: orr.w r7, r6, r7, lsl #26 +; CHECK-LLC-NEXT: orr.w r0, r0, r1, lsl #26 +; CHECK-LLC-NEXT: str r7, [r2] +; CHECK-LLC-NEXT: str r0, [r3] +; CHECK-LLC-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} +; CHECK-LCC: pop.w {r4, r5, r6, r7, r8, r9, r10, pc} +; +; CHECK-OPT-LABEL: @complex_dot_prod( +; CHECK-OPT-NEXT: entry: +; CHECK-OPT-NEXT: [[TMP0:%.*]] = bitcast i16* [[PSRCA:%.*]] to i32* +; CHECK-OPT-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 2 +; CHECK-OPT-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16 +; CHECK-OPT-NEXT: [[TMP3:%.*]] = sext i16 [[TMP2]] to i32 +; CHECK-OPT-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 16 +; CHECK-OPT-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16 +; CHECK-OPT-NEXT: [[TMP6:%.*]] = sext i16 [[TMP5]] to i32 +; CHECK-OPT-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds i16, i16* [[PSRCA]], i32 2 +; CHECK-OPT-NEXT: [[TMP7:%.*]] = bitcast i16* [[PSRCB:%.*]] to i32* +; CHECK-OPT-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 2 +; CHECK-OPT-NEXT: [[TMP9:%.*]] = trunc i32 [[TMP8]] to i16 +; CHECK-OPT-NEXT: [[TMP10:%.*]] = call i64 @llvm.arm.smlaldx(i32 [[TMP1]], i32 [[TMP8]], i64 0) +; CHECK-OPT-NEXT: [[TMP11:%.*]] = sext i16 [[TMP9]] to i32 +; CHECK-OPT-NEXT: [[TMP12:%.*]] = lshr i32 [[TMP8]], 16 +; CHECK-OPT-NEXT: [[TMP13:%.*]] = trunc i32 [[TMP12]] to i16 +; CHECK-OPT-NEXT: [[TMP14:%.*]] = sext i16 [[TMP13]] to i32 +; CHECK-OPT-NEXT: [[INCDEC_PTR3:%.*]] = getelementptr inbounds i16, i16* [[PSRCB]], i32 2 +; CHECK-OPT-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], [[TMP3]] +; CHECK-OPT-NEXT: [[CONV5:%.*]] = sext i32 [[MUL]] to i64 +; CHECK-OPT-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP14]], [[TMP6]] +; CHECK-OPT-NEXT: [[CONV14:%.*]] = sext i32 [[MUL13]] to i64 +; CHECK-OPT-NEXT: [[SUB:%.*]] = sub nsw i64 [[CONV5]], [[CONV14]] +; CHECK-OPT-NEXT: [[TMP15:%.*]] = bitcast i16* [[INCDEC_PTR1]] to i32* +; CHECK-OPT-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 2 +; CHECK-OPT-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i16 +; CHECK-OPT-NEXT: [[TMP18:%.*]] = sext i16 [[TMP17]] to i32 +; CHECK-OPT-NEXT: [[TMP19:%.*]] = lshr i32 [[TMP16]], 16 +; CHECK-OPT-NEXT: [[TMP20:%.*]] = trunc i32 [[TMP19]] to i16 +; CHECK-OPT-NEXT: [[TMP21:%.*]] = sext i16 [[TMP20]] to i32 +; CHECK-OPT-NEXT: [[INCDEC_PTR21:%.*]] = getelementptr inbounds i16, i16* [[PSRCA]], i32 4 +; CHECK-OPT-NEXT: [[TMP22:%.*]] = bitcast i16* [[INCDEC_PTR3]] to i32* +; CHECK-OPT-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 2 +; CHECK-OPT-NEXT: [[TMP24:%.*]] = trunc i32 [[TMP23]] to i16 +; CHECK-OPT-NEXT: [[TMP25:%.*]] = call i64 @llvm.arm.smlaldx(i32 [[TMP16]], i32 [[TMP23]], i64 [[TMP10]]) +; CHECK-OPT-NEXT: [[TMP26:%.*]] = sext i16 [[TMP24]] to i32 +; CHECK-OPT-NEXT: [[TMP27:%.*]] = lshr i32 [[TMP23]], 16 +; CHECK-OPT-NEXT: [[TMP28:%.*]] = trunc i32 [[TMP27]] to i16 +; CHECK-OPT-NEXT: [[TMP29:%.*]] = sext i16 [[TMP28]] to i32 +; CHECK-OPT-NEXT: [[INCDEC_PTR23:%.*]] = getelementptr inbounds i16, i16* [[PSRCB]], i32 4 +; CHECK-OPT-NEXT: [[MUL26:%.*]] = mul nsw i32 [[TMP26]], [[TMP18]] +; CHECK-OPT-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 +; CHECK-OPT-NEXT: [[ADD28:%.*]] = add nsw i64 [[SUB]], [[CONV27]] +; CHECK-OPT-NEXT: [[MUL36:%.*]] = mul nsw i32 [[TMP29]], [[TMP21]] +; CHECK-OPT-NEXT: [[CONV37:%.*]] = sext i32 [[MUL36]] to i64 +; CHECK-OPT-NEXT: [[SUB38:%.*]] = sub nsw i64 [[ADD28]], [[CONV37]] +; CHECK-OPT-NEXT: [[TMP30:%.*]] = bitcast i16* [[INCDEC_PTR21]] to i32* +; CHECK-OPT-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 2 +; CHECK-OPT-NEXT: [[TMP32:%.*]] = trunc i32 [[TMP31]] to i16 +; CHECK-OPT-NEXT: [[TMP33:%.*]] = sext i16 [[TMP32]] to i32 +; CHECK-OPT-NEXT: [[TMP34:%.*]] = lshr i32 [[TMP31]], 16 +; CHECK-OPT-NEXT: [[TMP35:%.*]] = trunc i32 [[TMP34]] to i16 +; CHECK-OPT-NEXT: [[TMP36:%.*]] = sext i16 [[TMP35]] to i32 +; CHECK-OPT-NEXT: [[INCDEC_PTR45:%.*]] = getelementptr inbounds i16, i16* [[PSRCA]], i32 6 +; CHECK-OPT-NEXT: [[TMP37:%.*]] = bitcast i16* [[INCDEC_PTR23]] to i32* +; CHECK-OPT-NEXT: [[TMP38:%.*]] = load i32, i32* [[TMP37]], align 2 +; CHECK-OPT-NEXT: [[TMP39:%.*]] = trunc i32 [[TMP38]] to i16 +; CHECK-OPT-NEXT: [[TMP40:%.*]] = call i64 @llvm.arm.smlaldx(i32 [[TMP31]], i32 [[TMP38]], i64 [[TMP25]]) +; CHECK-OPT-NEXT: [[TMP41:%.*]] = sext i16 [[TMP39]] to i32 +; CHECK-OPT-NEXT: [[TMP42:%.*]] = lshr i32 [[TMP38]], 16 +; CHECK-OPT-NEXT: [[TMP43:%.*]] = trunc i32 [[TMP42]] to i16 +; CHECK-OPT-NEXT: [[TMP44:%.*]] = sext i16 [[TMP43]] to i32 +; CHECK-OPT-NEXT: [[INCDEC_PTR47:%.*]] = getelementptr inbounds i16, i16* [[PSRCB]], i32 6 +; CHECK-OPT-NEXT: [[MUL50:%.*]] = mul nsw i32 [[TMP41]], [[TMP33]] +; CHECK-OPT-NEXT: [[CONV51:%.*]] = sext i32 [[MUL50]] to i64 +; CHECK-OPT-NEXT: [[ADD52:%.*]] = add nsw i64 [[SUB38]], [[CONV51]] +; CHECK-OPT-NEXT: [[MUL60:%.*]] = mul nsw i32 [[TMP44]], [[TMP36]] +; CHECK-OPT-NEXT: [[CONV61:%.*]] = sext i32 [[MUL60]] to i64 +; CHECK-OPT-NEXT: [[SUB62:%.*]] = sub nsw i64 [[ADD52]], [[CONV61]] +; CHECK-OPT-NEXT: [[TMP45:%.*]] = bitcast i16* [[INCDEC_PTR45]] to i32* +; CHECK-OPT-NEXT: [[TMP46:%.*]] = load i32, i32* [[TMP45]], align 2 +; CHECK-OPT-NEXT: [[TMP47:%.*]] = trunc i32 [[TMP46]] to i16 +; CHECK-OPT-NEXT: [[TMP48:%.*]] = sext i16 [[TMP47]] to i32 +; CHECK-OPT-NEXT: [[TMP49:%.*]] = lshr i32 [[TMP46]], 16 +; CHECK-OPT-NEXT: [[TMP50:%.*]] = trunc i32 [[TMP49]] to i16 +; CHECK-OPT-NEXT: [[TMP51:%.*]] = sext i16 [[TMP50]] to i32 +; CHECK-OPT-NEXT: [[TMP52:%.*]] = bitcast i16* [[INCDEC_PTR47]] to i32* +; CHECK-OPT-NEXT: [[TMP53:%.*]] = load i32, i32* [[TMP52]], align 2 +; CHECK-OPT-NEXT: [[TMP54:%.*]] = trunc i32 [[TMP53]] to i16 +; CHECK-OPT-NEXT: [[TMP55:%.*]] = call i64 @llvm.arm.smlaldx(i32 [[TMP46]], i32 [[TMP53]], i64 [[TMP40]]) +; CHECK-OPT-NEXT: [[TMP56:%.*]] = sext i16 [[TMP54]] to i32 +; CHECK-OPT-NEXT: [[TMP57:%.*]] = lshr i32 [[TMP53]], 16 +; CHECK-OPT-NEXT: [[TMP58:%.*]] = trunc i32 [[TMP57]] to i16 +; CHECK-OPT-NEXT: [[TMP59:%.*]] = sext i16 [[TMP58]] to i32 +; CHECK-OPT-NEXT: [[MUL74:%.*]] = mul nsw i32 [[TMP56]], [[TMP48]] +; CHECK-OPT-NEXT: [[CONV75:%.*]] = sext i32 [[MUL74]] to i64 +; CHECK-OPT-NEXT: [[ADD76:%.*]] = add nsw i64 [[SUB62]], [[CONV75]] +; CHECK-OPT-NEXT: [[MUL84:%.*]] = mul nsw i32 [[TMP59]], [[TMP51]] +; CHECK-OPT-NEXT: [[CONV85:%.*]] = sext i32 [[MUL84]] to i64 +; CHECK-OPT-NEXT: [[SUB86:%.*]] = sub nsw i64 [[ADD76]], [[CONV85]] +; CHECK-OPT-NEXT: [[TMP60:%.*]] = lshr i64 [[SUB86]], 6 +; CHECK-OPT-NEXT: [[CONV92:%.*]] = trunc i64 [[TMP60]] to i32 +; CHECK-OPT-NEXT: store i32 [[CONV92]], i32* [[REALRESULT:%.*]], align 4 +; CHECK-OPT-NEXT: [[TMP61:%.*]] = lshr i64 [[TMP55]], 6 +; CHECK-OPT-NEXT: [[CONV94:%.*]] = trunc i64 [[TMP61]] to i32 +; CHECK-OPT-NEXT: store i32 [[CONV94]], i32* [[IMAGRESULT:%.*]], align 4 +; CHECK-OPT-NEXT: ret void entry: %incdec.ptr = getelementptr inbounds i16, i16* %pSrcA, i32 1 %0 = load i16, i16* %pSrcA, align 2