From: Ville Syrjälä Date: Fri, 16 Dec 2022 00:38:00 +0000 (+0200) Subject: drm/i915/dsb: Align DSB register writes to 8 bytes X-Git-Tag: v6.6.7~1918^2~17^2~699 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3229319e446cafe51e8d3060bdf39203b95a5c98;p=platform%2Fkernel%2Flinux-starfive.git drm/i915/dsb: Align DSB register writes to 8 bytes Every DSB instruction has to be 8byte aligned. Make sure that is the case for the non-indexed register writes as well. The way this could end up unaligned is we emitted an odd number of indexed register writes beforehand. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20221216003810.13338-4-ville.syrjala@linux.intel.com Reviewed-by: Animesh Manna --- diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 90a22af..6abfd0f 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -172,6 +172,9 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, return; } + /* Every instruction should be 8 byte aligned. */ + dsb->free_pos = ALIGN(dsb->free_pos, 2); + dsb->ins_start_offset = dsb->free_pos; buf[dsb->free_pos++] = val; buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |