From: balazs.kilvady Date: Fri, 30 Jan 2015 19:13:22 +0000 (-0800) Subject: MIPS: Reland "Initial switch to Chromium-style CHECK_* and DCHECK_* macros.". X-Git-Tag: upstream/4.7.83~4673 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=320d42e58aed0dfbee4ac4721939aa6c3bbb4624;p=platform%2Fupstream%2Fv8.git MIPS: Reland "Initial switch to Chromium-style CHECK_* and DCHECK_* macros.". Port c65ae4f10c7273956e88db433f626b26a1377caf BUG= Review URL: https://codereview.chromium.org/892613003 Cr-Commit-Position: refs/heads/master@{#26367} --- diff --git a/src/compiler/mips/code-generator-mips.cc b/src/compiler/mips/code-generator-mips.cc index ada0337c5..c081f51bd 100644 --- a/src/compiler/mips/code-generator-mips.cc +++ b/src/compiler/mips/code-generator-mips.cc @@ -779,7 +779,7 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr, // Materialize a full 32-bit 1 or 0 value. The result register is always the // last output of the instruction. Label false_value; - DCHECK_NE(0, instr->OutputCount()); + DCHECK_NE(0u, instr->OutputCount()); Register result = i.OutputRegister(instr->OutputCount() - 1); Condition cc = kNoCondition; diff --git a/src/compiler/mips/instruction-selector-mips.cc b/src/compiler/mips/instruction-selector-mips.cc index d68401727..6eb29bce5 100644 --- a/src/compiler/mips/instruction-selector-mips.cc +++ b/src/compiler/mips/instruction-selector-mips.cc @@ -109,8 +109,8 @@ static void VisitBinop(InstructionSelector* selector, Node* node, outputs[output_count++] = g.DefineAsRegister(cont->result()); } - DCHECK_NE(0, input_count); - DCHECK_NE(0, output_count); + DCHECK_NE(0u, input_count); + DCHECK_NE(0u, output_count); DCHECK_GE(arraysize(inputs), input_count); DCHECK_GE(arraysize(outputs), output_count); diff --git a/src/compiler/mips64/code-generator-mips64.cc b/src/compiler/mips64/code-generator-mips64.cc index 559beead8..9fef60994 100644 --- a/src/compiler/mips64/code-generator-mips64.cc +++ b/src/compiler/mips64/code-generator-mips64.cc @@ -892,7 +892,7 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr, // Materialize a full 32-bit 1 or 0 value. The result register is always the // last output of the instruction. Label false_value; - DCHECK_NE(0, instr->OutputCount()); + DCHECK_NE(0u, instr->OutputCount()); Register result = i.OutputRegister(instr->OutputCount() - 1); Condition cc = kNoCondition; diff --git a/src/compiler/mips64/instruction-selector-mips64.cc b/src/compiler/mips64/instruction-selector-mips64.cc index c01d7403a..027276fe5 100644 --- a/src/compiler/mips64/instruction-selector-mips64.cc +++ b/src/compiler/mips64/instruction-selector-mips64.cc @@ -142,8 +142,8 @@ static void VisitBinop(InstructionSelector* selector, Node* node, outputs[output_count++] = g.DefineAsRegister(cont->result()); } - DCHECK_NE(0, input_count); - DCHECK_NE(0, output_count); + DCHECK_NE(0u, input_count); + DCHECK_NE(0u, output_count); DCHECK_GE(arraysize(inputs), input_count); DCHECK_GE(arraysize(outputs), output_count); diff --git a/src/ic/mips/ic-mips.cc b/src/ic/mips/ic-mips.cc index 0e8eb2c16..ea32f4e80 100644 --- a/src/ic/mips/ic-mips.cc +++ b/src/ic/mips/ic-mips.cc @@ -961,10 +961,10 @@ void PatchInlinedSmiCode(Address address, InlinedSmiCheck check) { Register reg = Register::from_code(Assembler::GetRs(instr_at_patch)); if (check == ENABLE_INLINED_SMI_CHECK) { DCHECK(Assembler::IsAndImmediate(instr_at_patch)); - DCHECK_EQ(0, Assembler::GetImmediate16(instr_at_patch)); + DCHECK_EQ(0u, Assembler::GetImmediate16(instr_at_patch)); patcher.masm()->andi(at, reg, kSmiTagMask); } else { - DCHECK(check == DISABLE_INLINED_SMI_CHECK); + DCHECK_EQ(check, DISABLE_INLINED_SMI_CHECK); DCHECK(Assembler::IsAndImmediate(instr_at_patch)); patcher.masm()->andi(at, reg, 0); } diff --git a/src/ic/mips64/ic-mips64.cc b/src/ic/mips64/ic-mips64.cc index 70aa38154..1c5efffda 100644 --- a/src/ic/mips64/ic-mips64.cc +++ b/src/ic/mips64/ic-mips64.cc @@ -961,10 +961,10 @@ void PatchInlinedSmiCode(Address address, InlinedSmiCheck check) { Register reg = Register::from_code(Assembler::GetRs(instr_at_patch)); if (check == ENABLE_INLINED_SMI_CHECK) { DCHECK(Assembler::IsAndImmediate(instr_at_patch)); - DCHECK_EQ(0, Assembler::GetImmediate16(instr_at_patch)); + DCHECK_EQ(0u, Assembler::GetImmediate16(instr_at_patch)); patcher.masm()->andi(at, reg, kSmiTagMask); } else { - DCHECK(check == DISABLE_INLINED_SMI_CHECK); + DCHECK_EQ(check, DISABLE_INLINED_SMI_CHECK); DCHECK(Assembler::IsAndImmediate(instr_at_patch)); patcher.masm()->andi(at, reg, 0); } diff --git a/src/mips/code-stubs-mips.cc b/src/mips/code-stubs-mips.cc index 5ce502cab..00d9c3c3f 100644 --- a/src/mips/code-stubs-mips.cc +++ b/src/mips/code-stubs-mips.cc @@ -588,7 +588,7 @@ void CompareICStub::GenerateGeneric(MacroAssembler* masm) { // If either is a Smi (we know that not both are), then they can only // be strictly equal if the other is a HeapNumber. STATIC_ASSERT(kSmiTag == 0); - DCHECK_EQ(0, Smi::FromInt(0)); + DCHECK_EQ(static_cast(0), Smi::FromInt(0)); __ And(t2, lhs, Operand(rhs)); __ JumpIfNotSmi(t2, ¬_smis, t0); // One operand is a smi. EmitSmiNonsmiComparison generates code that can: @@ -1465,7 +1465,7 @@ void InstanceofStub::Generate(MacroAssembler* masm) { __ Branch(&loop); __ bind(&is_instance); - DCHECK(Smi::FromInt(0) == 0); + DCHECK_EQ(static_cast(0), Smi::FromInt(0)); if (!HasCallSiteInlineCheck()) { __ mov(v0, zero_reg); __ StoreRoot(v0, Heap::kInstanceofCacheAnswerRootIndex); @@ -1480,7 +1480,6 @@ void InstanceofStub::Generate(MacroAssembler* masm) { __ PatchRelocatedValue(inline_site, scratch, v0); if (!ReturnTrueFalseObject()) { - DCHECK_EQ(Smi::FromInt(0), 0); __ mov(v0, zero_reg); } } @@ -1716,7 +1715,7 @@ void ArgumentsAccessStub::GenerateNewSloppyFast(MacroAssembler* masm) { FixedArray::kHeaderSize + 2 * kPointerSize; // If there are no mapped parameters, we do not need the parameter_map. Label param_map_size; - DCHECK_EQ(0, Smi::FromInt(0)); + DCHECK_EQ(static_cast(0), Smi::FromInt(0)); __ Branch(USE_DELAY_SLOT, ¶m_map_size, eq, a1, Operand(zero_reg)); __ mov(t5, zero_reg); // In delay slot: param map size = 0 when a1 == 0. __ sll(t5, a1, 1); diff --git a/src/mips/full-codegen-mips.cc b/src/mips/full-codegen-mips.cc index bd408d9b0..9fde09d80 100644 --- a/src/mips/full-codegen-mips.cc +++ b/src/mips/full-codegen-mips.cc @@ -1229,7 +1229,7 @@ void FullCodeGenerator::VisitForInStatement(ForInStatement* stmt) { // For proxies, no filtering is done. // TODO(rossberg): What if only a prototype is a proxy? Not specified yet. - DCHECK_EQ(Smi::FromInt(0), 0); + DCHECK_EQ(static_cast(0), Smi::FromInt(0)); __ Branch(&update_each, eq, a2, Operand(zero_reg)); // Convert the entry to a string or (smi) 0 if it isn't a property diff --git a/src/mips/macro-assembler-mips.cc b/src/mips/macro-assembler-mips.cc index c601657dd..5020692d0 100644 --- a/src/mips/macro-assembler-mips.cc +++ b/src/mips/macro-assembler-mips.cc @@ -3243,7 +3243,7 @@ void MacroAssembler::PushTryHandler(StackHandler::Kind kind, // Push the frame pointer, context, state, and code object. if (kind == StackHandler::JS_ENTRY) { - DCHECK_EQ(Smi::FromInt(0), 0); + DCHECK_EQ(static_cast(0), Smi::FromInt(0)); // The second zero_reg indicates no context. // The first zero_reg is the NULL frame pointer. // The operands are reversed to match the order of MultiPush/Pop. diff --git a/src/mips/macro-assembler-mips.h b/src/mips/macro-assembler-mips.h index 643b9b5e7..02845e2bb 100644 --- a/src/mips/macro-assembler-mips.h +++ b/src/mips/macro-assembler-mips.h @@ -1102,7 +1102,7 @@ class MacroAssembler: public Assembler { lw(type, FieldMemOperand(obj, HeapObject::kMapOffset)); lbu(type, FieldMemOperand(type, Map::kInstanceTypeOffset)); And(type, type, Operand(kIsNotStringMask)); - DCHECK_EQ(0, kStringTag); + DCHECK_EQ(0u, kStringTag); return eq; } diff --git a/src/mips64/code-stubs-mips64.cc b/src/mips64/code-stubs-mips64.cc index 441940970..05bf5f152 100644 --- a/src/mips64/code-stubs-mips64.cc +++ b/src/mips64/code-stubs-mips64.cc @@ -583,7 +583,7 @@ void CompareICStub::GenerateGeneric(MacroAssembler* masm) { // If either is a Smi (we know that not both are), then they can only // be strictly equal if the other is a HeapNumber. STATIC_ASSERT(kSmiTag == 0); - DCHECK_EQ(0, Smi::FromInt(0)); + DCHECK_EQ(static_cast(0), Smi::FromInt(0)); __ And(a6, lhs, Operand(rhs)); __ JumpIfNotSmi(a6, ¬_smis, a4); // One operand is a smi. EmitSmiNonsmiComparison generates code that can: @@ -1465,7 +1465,7 @@ void InstanceofStub::Generate(MacroAssembler* masm) { __ Branch(&loop); __ bind(&is_instance); - DCHECK(Smi::FromInt(0) == 0); + DCHECK_EQ(static_cast(0), Smi::FromInt(0)); if (!HasCallSiteInlineCheck()) { __ mov(v0, zero_reg); __ StoreRoot(v0, Heap::kInstanceofCacheAnswerRootIndex); @@ -1480,7 +1480,6 @@ void InstanceofStub::Generate(MacroAssembler* masm) { __ PatchRelocatedValue(inline_site, scratch, v0); if (!ReturnTrueFalseObject()) { - DCHECK_EQ(Smi::FromInt(0), 0); __ mov(v0, zero_reg); } } @@ -1715,7 +1714,7 @@ void ArgumentsAccessStub::GenerateNewSloppyFast(MacroAssembler* masm) { FixedArray::kHeaderSize + 2 * kPointerSize; // If there are no mapped parameters, we do not need the parameter_map. Label param_map_size; - DCHECK_EQ(0, Smi::FromInt(0)); + DCHECK_EQ(static_cast(0), Smi::FromInt(0)); __ Branch(USE_DELAY_SLOT, ¶m_map_size, eq, a1, Operand(zero_reg)); __ mov(t1, zero_reg); // In delay slot: param map size = 0 when a1 == 0. __ SmiScale(t1, a1, kPointerSizeLog2); diff --git a/src/mips64/full-codegen-mips64.cc b/src/mips64/full-codegen-mips64.cc index 9e79bcbb5..eccd1f923 100644 --- a/src/mips64/full-codegen-mips64.cc +++ b/src/mips64/full-codegen-mips64.cc @@ -1224,7 +1224,7 @@ void FullCodeGenerator::VisitForInStatement(ForInStatement* stmt) { // For proxies, no filtering is done. // TODO(rossberg): What if only a prototype is a proxy? Not specified yet. - DCHECK_EQ(Smi::FromInt(0), 0); + DCHECK_EQ(static_cast(0), Smi::FromInt(0)); __ Branch(&update_each, eq, a2, Operand(zero_reg)); // Convert the entry to a string or (smi) 0 if it isn't a property diff --git a/src/mips64/macro-assembler-mips64.cc b/src/mips64/macro-assembler-mips64.cc index 21cc3dc1e..8b00f0276 100644 --- a/src/mips64/macro-assembler-mips64.cc +++ b/src/mips64/macro-assembler-mips64.cc @@ -3234,7 +3234,7 @@ void MacroAssembler::PushTryHandler(StackHandler::Kind kind, // Push the frame pointer, context, state, and code object. if (kind == StackHandler::JS_ENTRY) { - DCHECK_EQ(Smi::FromInt(0), 0); + DCHECK_EQ(static_cast(0), Smi::FromInt(0)); // The second zero_reg indicates no context. // The first zero_reg is the NULL frame pointer. // The operands are reversed to match the order of MultiPush/Pop. @@ -5222,7 +5222,7 @@ void MacroAssembler::JumpIfNotBothSmi(Register reg1, #if defined(__APPLE__) DCHECK_EQ(1, kSmiTagMask); #else - DCHECK_EQ((uint64_t)1, kSmiTagMask); + DCHECK_EQ((int64_t)1, kSmiTagMask); #endif or_(at, reg1, reg2); JumpIfNotSmi(at, on_not_both_smi); @@ -5237,7 +5237,7 @@ void MacroAssembler::JumpIfEitherSmi(Register reg1, #if defined(__APPLE__) DCHECK_EQ(1, kSmiTagMask); #else - DCHECK_EQ((uint64_t)1, kSmiTagMask); + DCHECK_EQ((int64_t)1, kSmiTagMask); #endif // Both Smi tags must be 1 (not Smi). and_(at, reg1, reg2); diff --git a/src/mips64/macro-assembler-mips64.h b/src/mips64/macro-assembler-mips64.h index cf0becec7..1e25b334c 100644 --- a/src/mips64/macro-assembler-mips64.h +++ b/src/mips64/macro-assembler-mips64.h @@ -1132,7 +1132,7 @@ class MacroAssembler: public Assembler { ld(type, FieldMemOperand(obj, HeapObject::kMapOffset)); lbu(type, FieldMemOperand(type, Map::kInstanceTypeOffset)); And(type, type, Operand(kIsNotStringMask)); - DCHECK_EQ(0, kStringTag); + DCHECK_EQ(0u, kStringTag); return eq; } diff --git a/src/mips64/simulator-mips64.cc b/src/mips64/simulator-mips64.cc index 883991768..bb39b97cc 100644 --- a/src/mips64/simulator-mips64.cc +++ b/src/mips64/simulator-mips64.cc @@ -809,7 +809,7 @@ void Simulator::FlushICache(v8::internal::HashMap* i_cache, FlushOnePage(i_cache, start, bytes_to_flush); start += bytes_to_flush; size -= bytes_to_flush; - DCHECK_EQ((uint64_t)0, start & CachePage::kPageMask); + DCHECK_EQ((int64_t)0, start & CachePage::kPageMask); offset = 0; } if (size != 0) { diff --git a/test/cctest/test-assembler-mips.cc b/test/cctest/test-assembler-mips.cc index 74dcc3a0a..4809387c0 100644 --- a/test/cctest/test-assembler-mips.cc +++ b/test/cctest/test-assembler-mips.cc @@ -66,7 +66,7 @@ TEST(MIPS0) { F2 f = FUNCTION_CAST(code->entry()); int res = reinterpret_cast(CALL_GENERATED_CODE(f, 0xab0, 0xc, 0, 0, 0)); ::printf("f() = %d\n", res); - CHECK_EQ(0xabc, res); + CHECK_EQ(static_cast(0xabc), res); } @@ -240,7 +240,7 @@ TEST(MIPS2) { F2 f = FUNCTION_CAST(code->entry()); int res = reinterpret_cast(CALL_GENERATED_CODE(f, 0xab0, 0xc, 0, 0, 0)); ::printf("f() = %d\n", res); - CHECK_EQ(0x31415926, res); + CHECK_EQ(static_cast(0x31415926), res); } @@ -523,19 +523,19 @@ TEST(MIPS6) { Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0); USE(dummy); - CHECK_EQ(0x11223344, t.r1); + CHECK_EQ(static_cast(0x11223344), t.r1); #if __BYTE_ORDER == __LITTLE_ENDIAN - CHECK_EQ(0x3344, t.r2); - CHECK_EQ(0xffffbbcc, t.r3); - CHECK_EQ(0x0000bbcc, t.r4); - CHECK_EQ(0xffffffcc, t.r5); - CHECK_EQ(0x3333bbcc, t.r6); + CHECK_EQ(static_cast(0x3344), t.r2); + CHECK_EQ(static_cast(0xffffbbcc), t.r3); + CHECK_EQ(static_cast(0x0000bbcc), t.r4); + CHECK_EQ(static_cast(0xffffffcc), t.r5); + CHECK_EQ(static_cast(0x3333bbcc), t.r6); #elif __BYTE_ORDER == __BIG_ENDIAN - CHECK_EQ(0x1122, t.r2); - CHECK_EQ(0xffff99aa, t.r3); - CHECK_EQ(0x000099aa, t.r4); - CHECK_EQ(0xffffff99, t.r5); - CHECK_EQ(0x99aa3333, t.r6); + CHECK_EQ(static_cast(0x1122), t.r2); + CHECK_EQ(static_cast(0xffff99aa), t.r3); + CHECK_EQ(static_cast(0x000099aa), t.r4); + CHECK_EQ(static_cast(0xffffff99), t.r5); + CHECK_EQ(static_cast(0x99aa3333), t.r6); #else #error Unknown endianness #endif @@ -710,21 +710,21 @@ TEST(MIPS8) { t.input = 0x12345678; Object* dummy = CALL_GENERATED_CODE(f, &t, 0x0, 0, 0, 0); USE(dummy); - CHECK_EQ(0x81234567, t.result_rotr_4); - CHECK_EQ(0x78123456, t.result_rotr_8); - CHECK_EQ(0x67812345, t.result_rotr_12); - CHECK_EQ(0x56781234, t.result_rotr_16); - CHECK_EQ(0x45678123, t.result_rotr_20); - CHECK_EQ(0x34567812, t.result_rotr_24); - CHECK_EQ(0x23456781, t.result_rotr_28); - - CHECK_EQ(0x81234567, t.result_rotrv_4); - CHECK_EQ(0x78123456, t.result_rotrv_8); - CHECK_EQ(0x67812345, t.result_rotrv_12); - CHECK_EQ(0x56781234, t.result_rotrv_16); - CHECK_EQ(0x45678123, t.result_rotrv_20); - CHECK_EQ(0x34567812, t.result_rotrv_24); - CHECK_EQ(0x23456781, t.result_rotrv_28); + CHECK_EQ(static_cast(0x81234567), t.result_rotr_4); + CHECK_EQ(static_cast(0x78123456), t.result_rotr_8); + CHECK_EQ(static_cast(0x67812345), t.result_rotr_12); + CHECK_EQ(static_cast(0x56781234), t.result_rotr_16); + CHECK_EQ(static_cast(0x45678123), t.result_rotr_20); + CHECK_EQ(static_cast(0x34567812), t.result_rotr_24); + CHECK_EQ(static_cast(0x23456781), t.result_rotr_28); + + CHECK_EQ(static_cast(0x81234567), t.result_rotrv_4); + CHECK_EQ(static_cast(0x78123456), t.result_rotrv_8); + CHECK_EQ(static_cast(0x67812345), t.result_rotrv_12); + CHECK_EQ(static_cast(0x56781234), t.result_rotrv_16); + CHECK_EQ(static_cast(0x45678123), t.result_rotrv_20); + CHECK_EQ(static_cast(0x34567812), t.result_rotrv_24); + CHECK_EQ(static_cast(0x23456781), t.result_rotrv_28); } @@ -809,9 +809,9 @@ TEST(MIPS10) { Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0); USE(dummy); - CHECK_EQ(0x41DFFFFF, t.dbl_exp); - CHECK_EQ(0xFF800000, t.dbl_mant); - CHECK_EQ(0X7FFFFFFE, t.word); + CHECK_EQ(static_cast(0x41DFFFFF), t.dbl_exp); + CHECK_EQ(static_cast(0xFF800000), t.dbl_mant); + CHECK_EQ(static_cast(0x7FFFFFFE), t.word); // 0x0FF00FF0 -> 2.6739096+e08 CHECK_EQ(2.6739096e08, t.b); } @@ -940,45 +940,45 @@ TEST(MIPS11) { USE(dummy); #if __BYTE_ORDER == __LITTLE_ENDIAN - CHECK_EQ(0x44bbccdd, t.lwl_0); - CHECK_EQ(0x3344ccdd, t.lwl_1); - CHECK_EQ(0x223344dd, t.lwl_2); - CHECK_EQ(0x11223344, t.lwl_3); - - CHECK_EQ(0x11223344, t.lwr_0); - CHECK_EQ(0xaa112233, t.lwr_1); - CHECK_EQ(0xaabb1122, t.lwr_2); - CHECK_EQ(0xaabbcc11, t.lwr_3); - - CHECK_EQ(0x112233aa, t.swl_0); - CHECK_EQ(0x1122aabb, t.swl_1); - CHECK_EQ(0x11aabbcc, t.swl_2); - CHECK_EQ(0xaabbccdd, t.swl_3); - - CHECK_EQ(0xaabbccdd, t.swr_0); - CHECK_EQ(0xbbccdd44, t.swr_1); - CHECK_EQ(0xccdd3344, t.swr_2); - CHECK_EQ(0xdd223344, t.swr_3); + CHECK_EQ(static_cast(0x44bbccdd), t.lwl_0); + CHECK_EQ(static_cast(0x3344ccdd), t.lwl_1); + CHECK_EQ(static_cast(0x223344dd), t.lwl_2); + CHECK_EQ(static_cast(0x11223344), t.lwl_3); + + CHECK_EQ(static_cast(0x11223344), t.lwr_0); + CHECK_EQ(static_cast(0xaa112233), t.lwr_1); + CHECK_EQ(static_cast(0xaabb1122), t.lwr_2); + CHECK_EQ(static_cast(0xaabbcc11), t.lwr_3); + + CHECK_EQ(static_cast(0x112233aa), t.swl_0); + CHECK_EQ(static_cast(0x1122aabb), t.swl_1); + CHECK_EQ(static_cast(0x11aabbcc), t.swl_2); + CHECK_EQ(static_cast(0xaabbccdd), t.swl_3); + + CHECK_EQ(static_cast(0xaabbccdd), t.swr_0); + CHECK_EQ(static_cast(0xbbccdd44), t.swr_1); + CHECK_EQ(static_cast(0xccdd3344), t.swr_2); + CHECK_EQ(static_cast(0xdd223344), t.swr_3); #elif __BYTE_ORDER == __BIG_ENDIAN - CHECK_EQ(0x11223344, t.lwl_0); - CHECK_EQ(0x223344dd, t.lwl_1); - CHECK_EQ(0x3344ccdd, t.lwl_2); - CHECK_EQ(0x44bbccdd, t.lwl_3); - - CHECK_EQ(0xaabbcc11, t.lwr_0); - CHECK_EQ(0xaabb1122, t.lwr_1); - CHECK_EQ(0xaa112233, t.lwr_2); - CHECK_EQ(0x11223344, t.lwr_3); - - CHECK_EQ(0xaabbccdd, t.swl_0); - CHECK_EQ(0x11aabbcc, t.swl_1); - CHECK_EQ(0x1122aabb, t.swl_2); - CHECK_EQ(0x112233aa, t.swl_3); - - CHECK_EQ(0xdd223344, t.swr_0); - CHECK_EQ(0xccdd3344, t.swr_1); - CHECK_EQ(0xbbccdd44, t.swr_2); - CHECK_EQ(0xaabbccdd, t.swr_3); + 11223344, t.lwl_0); + CHECK_EQ(static_cast(0x223344dd), t.lwl_1); + CHECK_EQ(static_cast(0x3344ccdd), t.lwl_2); + CHECK_EQ(static_cast(0x44bbccdd), t.lwl_3); + + CHECK_EQ(static_cast(0xaabbcc11), t.lwr_0); + CHECK_EQ(static_cast(0xaabb1122), t.lwr_1); + CHECK_EQ(static_cast(0xaa112233), t.lwr_2); + CHECK_EQ(static_cast(0x11223344), t.lwr_3); + + CHECK_EQ(static_cast(0xaabbccdd), t.swl_0); + CHECK_EQ(static_cast(0x11aabbcc), t.swl_1); + CHECK_EQ(static_cast(0x1122aabb), t.swl_2); + CHECK_EQ(static_cast(0x112233aa), t.swl_3); + + CHECK_EQ(static_cast(0xdd223344), t.swr_0); + CHECK_EQ(static_cast(0xccdd3344), t.swr_1); + CHECK_EQ(static_cast(0xbbccdd44), t.swr_2); + CHECK_EQ(static_cast(0xaabbccdd), t.swr_3); #else #error Unknown endianness #endif @@ -1245,12 +1245,12 @@ TEST(MIPS14) { USE(dummy); #define GET_FPU_ERR(x) (static_cast(x & kFCSRFlagMask)) -#define CHECK_ROUND_RESULT(type) \ - CHECK(GET_FPU_ERR(t.type##_err1_out) & kFCSRInexactFlagMask); \ - CHECK_EQ(0, GET_FPU_ERR(t.type##_err2_out)); \ +#define CHECK_ROUND_RESULT(type) \ + CHECK(GET_FPU_ERR(t.type##_err1_out) & kFCSRInexactFlagMask); \ + CHECK_EQ(0, GET_FPU_ERR(t.type##_err2_out)); \ CHECK(GET_FPU_ERR(t.type##_err3_out) & kFCSRInvalidOpFlagMask); \ CHECK(GET_FPU_ERR(t.type##_err4_out) & kFCSRInvalidOpFlagMask); \ - CHECK_EQ(kFPUInvalidResult, t.type##_invalid_result); + CHECK_EQ(kFPUInvalidResult, static_cast(t.type##_invalid_result)); CHECK_ROUND_RESULT(round); CHECK_ROUND_RESULT(floor); diff --git a/test/cctest/test-assembler-mips64.cc b/test/cctest/test-assembler-mips64.cc index 1ec9a65c9..5edacd790 100644 --- a/test/cctest/test-assembler-mips64.cc +++ b/test/cctest/test-assembler-mips64.cc @@ -407,8 +407,8 @@ TEST(MIPS4) { CHECK_EQ(2.75e11, t.a); CHECK_EQ(2.75e11, t.b); CHECK_EQ(1.5e22, t.c); - CHECK_EQ(0xffffffffc25001d1L, t.high); - CHECK_EQ(0xffffffffbf800000L, t.low); + CHECK_EQ(static_cast(0xffffffffc25001d1L), t.high); + CHECK_EQ(static_cast(0xffffffffbf800000L), t.low); } @@ -538,12 +538,12 @@ TEST(MIPS6) { Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0); USE(dummy); - CHECK_EQ(0x11223344, t.r1); - CHECK_EQ(0x3344, t.r2); - CHECK_EQ(0xffffbbcc, t.r3); - CHECK_EQ(0x0000bbcc, t.r4); - CHECK_EQ(0xffffffcc, t.r5); - CHECK_EQ(0x3333bbcc, t.r6); + CHECK_EQ(static_cast(0x11223344), t.r1); + CHECK_EQ(static_cast(0x3344), t.r2); + CHECK_EQ(static_cast(0xffffbbcc), t.r3); + CHECK_EQ(static_cast(0x0000bbcc), t.r4); + CHECK_EQ(static_cast(0xffffffcc), t.r5); + CHECK_EQ(static_cast(0x3333bbcc), t.r6); } @@ -712,21 +712,21 @@ TEST(MIPS8) { t.input = 0x12345678; Object* dummy = CALL_GENERATED_CODE(f, &t, 0x0, 0, 0, 0); USE(dummy); - CHECK_EQ(0x81234567, t.result_rotr_4); - CHECK_EQ(0x78123456, t.result_rotr_8); - CHECK_EQ(0x67812345, t.result_rotr_12); - CHECK_EQ(0x56781234, t.result_rotr_16); - CHECK_EQ(0x45678123, t.result_rotr_20); - CHECK_EQ(0x34567812, t.result_rotr_24); - CHECK_EQ(0x23456781, t.result_rotr_28); - - CHECK_EQ(0x81234567, t.result_rotrv_4); - CHECK_EQ(0x78123456, t.result_rotrv_8); - CHECK_EQ(0x67812345, t.result_rotrv_12); - CHECK_EQ(0x56781234, t.result_rotrv_16); - CHECK_EQ(0x45678123, t.result_rotrv_20); - CHECK_EQ(0x34567812, t.result_rotrv_24); - CHECK_EQ(0x23456781, t.result_rotrv_28); + CHECK_EQ(static_cast(0x81234567), t.result_rotr_4); + CHECK_EQ(static_cast(0x78123456), t.result_rotr_8); + CHECK_EQ(static_cast(0x67812345), t.result_rotr_12); + CHECK_EQ(static_cast(0x56781234), t.result_rotr_16); + CHECK_EQ(static_cast(0x45678123), t.result_rotr_20); + CHECK_EQ(static_cast(0x34567812), t.result_rotr_24); + CHECK_EQ(static_cast(0x23456781), t.result_rotr_28); + + CHECK_EQ(static_cast(0x81234567), t.result_rotrv_4); + CHECK_EQ(static_cast(0x78123456), t.result_rotrv_8); + CHECK_EQ(static_cast(0x67812345), t.result_rotrv_12); + CHECK_EQ(static_cast(0x56781234), t.result_rotrv_16); + CHECK_EQ(static_cast(0x45678123), t.result_rotrv_20); + CHECK_EQ(static_cast(0x34567812), t.result_rotrv_24); + CHECK_EQ(static_cast(0x23456781), t.result_rotrv_28); } @@ -838,15 +838,15 @@ TEST(MIPS10) { Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0); USE(dummy); - CHECK_EQ(0x41DFFFFF, t.dbl_exp); - CHECK_EQ(0xFFC00000, t.dbl_mant); + CHECK_EQ(static_cast(0x41DFFFFF), t.dbl_exp); + CHECK_EQ(static_cast(0xFFC00000), t.dbl_mant); CHECK_EQ(0, t.long_hi); - CHECK_EQ(0x7fffffff, t.long_lo); + CHECK_EQ(static_cast(0x7fffffff), t.long_lo); CHECK_EQ(2.147483647e9, t.a_converted); // 0xFF00FF00FF -> 1.095233372415e12. CHECK_EQ(1.095233372415e12, t.b); - CHECK_EQ(0xFF00FF00FF, t.b_long_as_int64); + CHECK_EQ(static_cast(0xFF00FF00FF), t.b_long_as_int64); } } @@ -973,25 +973,25 @@ TEST(MIPS11) { Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0); USE(dummy); - CHECK_EQ(0x44bbccdd, t.lwl_0); - CHECK_EQ(0x3344ccdd, t.lwl_1); - CHECK_EQ(0x223344dd, t.lwl_2); - CHECK_EQ(0x11223344, t.lwl_3); - - CHECK_EQ(0x11223344, t.lwr_0); - CHECK_EQ(0xaa112233, t.lwr_1); - CHECK_EQ(0xaabb1122, t.lwr_2); - CHECK_EQ(0xaabbcc11, t.lwr_3); - - CHECK_EQ(0x112233aa, t.swl_0); - CHECK_EQ(0x1122aabb, t.swl_1); - CHECK_EQ(0x11aabbcc, t.swl_2); - CHECK_EQ(0xaabbccdd, t.swl_3); - - CHECK_EQ(0xaabbccdd, t.swr_0); - CHECK_EQ(0xbbccdd44, t.swr_1); - CHECK_EQ(0xccdd3344, t.swr_2); - CHECK_EQ(0xdd223344, t.swr_3); + CHECK_EQ(static_cast(0x44bbccdd), t.lwl_0); + CHECK_EQ(static_cast(0x3344ccdd), t.lwl_1); + CHECK_EQ(static_cast(0x223344dd), t.lwl_2); + CHECK_EQ(static_cast(0x11223344), t.lwl_3); + + CHECK_EQ(static_cast(0x11223344), t.lwr_0); + CHECK_EQ(static_cast(0xaa112233), t.lwr_1); + CHECK_EQ(static_cast(0xaabb1122), t.lwr_2); + CHECK_EQ(static_cast(0xaabbcc11), t.lwr_3); + + CHECK_EQ(static_cast(0x112233aa), t.swl_0); + CHECK_EQ(static_cast(0x1122aabb), t.swl_1); + CHECK_EQ(static_cast(0x11aabbcc), t.swl_2); + CHECK_EQ(static_cast(0xaabbccdd), t.swl_3); + + CHECK_EQ(static_cast(0xaabbccdd), t.swr_0); + CHECK_EQ(static_cast(0xbbccdd44), t.swr_1); + CHECK_EQ(static_cast(0xccdd3344), t.swr_2); + CHECK_EQ(static_cast(0xdd223344), t.swr_3); } } @@ -1374,16 +1374,16 @@ TEST(MIPS16) { USE(dummy); // Unsigned data, 32 & 64. - CHECK_EQ(0x1111111144332211L, t.r1); - CHECK_EQ(0x0000000000002211L, t.r2); + CHECK_EQ(static_cast(0x1111111144332211L), t.r1); + CHECK_EQ(static_cast(0x0000000000002211L), t.r2); // Signed data, 32 & 64. - CHECK_EQ(0x33333333ffffbbccL, t.r3); - CHECK_EQ(0xffffffff0000bbccL, t.r4); + CHECK_EQ(static_cast(0x33333333ffffbbccL), t.r3); + CHECK_EQ(static_cast(0xffffffff0000bbccL), t.r4); // Signed data, 32 & 64. - CHECK_EQ(0x55555555ffffffccL, t.r5); - CHECK_EQ(0x000000003333bbccL, t.r6); + CHECK_EQ(static_cast(0x55555555ffffffccL), t.r5); + CHECK_EQ(static_cast(0x000000003333bbccL), t.r6); } #undef __