From: samin <samin.guo@starfivetech.com>
Date: Wed, 22 Dec 2021 07:34:41 +0000 (+0800)
Subject: dt-bingings:reset: Add reset node for vdec&&jpeg.
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=31e4a8cda4b5216582ba44519174fbd41f7e9662;p=platform%2Fkernel%2Flinux-starfive.git

dt-bingings:reset: Add reset node for vdec&&jpeg.

Add reset bindings for the vdec&jpeg.

Signed-off-by: samin <samin.guo@starfivetech.com>
---

diff --git a/arch/riscv/boot/dts/starfive/starfive_jh7110.dts b/arch/riscv/boot/dts/starfive/starfive_jh7110.dts
index 906d13e..03ca8e51 100644
--- a/arch/riscv/boot/dts/starfive/starfive_jh7110.dts
+++ b/arch/riscv/boot/dts/starfive/starfive_jh7110.dts
@@ -540,6 +540,12 @@
 		    interrupts = <14>;
 		    clocks = <&jpuclk>;
 		    clock-names = "axi_clk", "core_clk", "apb_clk";
+			resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
+				<&rstgen RSTN_U0_CODAJ12_CORE>,
+				<&rstgen RSTN_U0_CODAJ12_APB>;
+			reset-names = "rst_axi",
+				"rst_core",
+				"rst_apb";
 		    status = "okay";
 		};
 
@@ -555,6 +561,16 @@
 				"apb_clk",
 				"aximem_128b";
 		    //starfive,vdec_noc_ctrl;
+		    resets = <&rstgen RSTN_U0_WAVE511_AXI>,
+				<&rstgen RSTN_U0_WAVE511_BPU>,
+				<&rstgen RSTN_U0_WAVE511_VCE>,
+				<&rstgen RSTN_U0_WAVE511_APB>,
+				<&rstgen RSTN_U0_AXIMEM_128B_AXI>;
+		    reset-names = "rst_axi",
+				"rst_bpu",
+				"rst_vce",
+				"rst_apb",
+				"rst_sram";
 		    status = "okay";
 		};
 		vpu_enc:vpu_enc@130B0000 {