From: Richard Biener Date: Thu, 12 Nov 2015 14:02:44 +0000 (+0000) Subject: re PR tree-optimization/68306 (ICE: in vectorizable_store, at tree-vect-stmts.c:5651) X-Git-Tag: upstream/12.2.0~50935 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=31271e9129c949aeb4628021a34191d696d75e34;p=platform%2Fupstream%2Fgcc.git re PR tree-optimization/68306 (ICE: in vectorizable_store, at tree-vect-stmts.c:5651) 2015-11-12 Richard Biener PR tree-optimization/68306 * tree-vect-data-refs.c (verify_data_ref_alignment): Remove relevant and vectorizable checks here. (vect_verify_datarefs_alignment): Add relevant check here. * gcc.dg/pr68306.c: New testcase. From-SVN: r230260 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7089985..ecd3711 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2015-11-12 Richard Biener + + PR tree-optimization/68306 + * tree-vect-data-refs.c (verify_data_ref_alignment): Remove + relevant and vectorizable checks here. + (vect_verify_datarefs_alignment): Add relevant check here. + 2015-11-12 Nathan Sidwell gcc/ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ace9cfd..7d32ad8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-11-12 Richard Biener + + PR tree-optimization/68306 + * gcc.dg/pr68306.c: New testcase. + 2015-11-12 Ville Voutilainen Implement D0013R2, logical type traits. diff --git a/gcc/testsuite/gcc.dg/pr68306.c b/gcc/testsuite/gcc.dg/pr68306.c new file mode 100644 index 0000000..b36fb34 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr68306.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +enum powerpc_pmc_type { PPC_PMC_IBM }; +struct { + unsigned num_pmcs; + enum powerpc_pmc_type pmc_type; +} a; +enum powerpc_pmc_type b; +void fn1() { a.num_pmcs = a.pmc_type = b; } diff --git a/gcc/tree-vect-data-refs.c b/gcc/tree-vect-data-refs.c index f7471b8..da5b2e9 100644 --- a/gcc/tree-vect-data-refs.c +++ b/gcc/tree-vect-data-refs.c @@ -909,14 +909,9 @@ verify_data_ref_alignment (data_reference_p dr) gimple *stmt = DR_STMT (dr); stmt_vec_info stmt_info = vinfo_for_stmt (stmt); - if (!STMT_VINFO_RELEVANT_P (stmt_info)) - return true; - - /* For interleaving, only the alignment of the first access matters. - Skip statements marked as not vectorizable. */ - if ((STMT_VINFO_GROUPED_ACCESS (stmt_info) - && GROUP_FIRST_ELEMENT (stmt_info) != stmt) - || !STMT_VINFO_VECTORIZABLE (stmt_info)) + /* For interleaving, only the alignment of the first access matters. */ + if (STMT_VINFO_GROUPED_ACCESS (stmt_info) + && GROUP_FIRST_ELEMENT (stmt_info) != stmt) return true; /* Strided accesses perform only component accesses, alignment is @@ -965,8 +960,15 @@ vect_verify_datarefs_alignment (loop_vec_info vinfo) unsigned int i; FOR_EACH_VEC_ELT (datarefs, i, dr) - if (! verify_data_ref_alignment (dr)) - return false; + { + gimple *stmt = DR_STMT (dr); + stmt_vec_info stmt_info = vinfo_for_stmt (stmt); + + if (!STMT_VINFO_RELEVANT_P (stmt_info)) + continue; + if (! verify_data_ref_alignment (dr)) + return false; + } return true; }