From: Aditya Nandakumar Date: Thu, 13 Nov 2014 21:29:21 +0000 (+0000) Subject: We can get the TLOF from the TargetMachine - so constructor no longer requires Target... X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=3053155652cf1d1c3f82f230fe62fd4c1c80b9d4;p=platform%2Fupstream%2Fllvm.git We can get the TLOF from the TargetMachine - so constructor no longer requires TargetLoweringObjectFile to be passed. llvm-svn: 221926 --- diff --git a/llvm/include/llvm/Target/TargetLowering.h b/llvm/include/llvm/Target/TargetLowering.h index 09b4662..882dab4 100644 --- a/llvm/include/llvm/Target/TargetLowering.h +++ b/llvm/include/llvm/Target/TargetLowering.h @@ -138,8 +138,7 @@ public: } /// NOTE: The TargetMachine owns TLOF. - explicit TargetLoweringBase(const TargetMachine &TM, - const TargetLoweringObjectFile *TLOF); + explicit TargetLoweringBase(const TargetMachine &TM); virtual ~TargetLoweringBase() {} protected: @@ -149,7 +148,9 @@ protected: public: const TargetMachine &getTargetMachine() const { return TM; } const DataLayout *getDataLayout() const { return DL; } - const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } + const TargetLoweringObjectFile &getObjFileLowering() const { + return *TM.getObjFileLowering(); + } bool isBigEndian() const { return !IsLittleEndian; } bool isLittleEndian() const { return IsLittleEndian; } @@ -1554,7 +1555,6 @@ public: private: const TargetMachine &TM; const DataLayout *DL; - const TargetLoweringObjectFile &TLOF; /// True if this is a little endian target. bool IsLittleEndian; @@ -1964,9 +1964,8 @@ class TargetLowering : public TargetLoweringBase { void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION; public: - /// NOTE: The constructor takes ownership of TLOF. - explicit TargetLowering(const TargetMachine &TM, - const TargetLoweringObjectFile *TLOF); + /// NOTE: The TargetMachine owns TLOF. + explicit TargetLowering(const TargetMachine &TM); /// Returns true by value, base pointer and offset pointer and addressing mode /// by reference if the node's address can be legally represented as diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 4fbe672..9aef5ed 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -35,10 +35,9 @@ #include using namespace llvm; -/// NOTE: The constructor takes ownership of TLOF. -TargetLowering::TargetLowering(const TargetMachine &tm, - const TargetLoweringObjectFile *tlof) - : TargetLoweringBase(tm, tlof) {} +/// NOTE: The TargetMachine owns TLOF. +TargetLowering::TargetLowering(const TargetMachine &tm) + : TargetLoweringBase(tm) {} const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { return nullptr; diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index 6d499e3..ffb8759 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -694,10 +694,9 @@ static void InitCmpLibcallCCs(ISD::CondCode *CCs) { CCs[RTLIB::O_F128] = ISD::SETEQ; } -/// NOTE: The constructor takes ownership of TLOF. -TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm, - const TargetLoweringObjectFile *tlof) - : TM(tm), DL(TM.getSubtargetImpl()->getDataLayout()), TLOF(*tlof) { +/// NOTE: The TargetMachine owns TLOF. +TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) + : TM(tm), DL(TM.getSubtargetImpl()->getDataLayout()) { initActions(); // Perform these initializations only once. diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index b600cb0..04ea60c 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -68,7 +68,7 @@ EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden, AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM) - : TargetLowering(TM, TM.getObjFileLowering()) { + : TargetLowering(TM) { Subtarget = &TM.getSubtarget(); // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 337ceef..a7a6ddd 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -157,7 +157,7 @@ void ARMTargetLowering::addQRTypeForNEON(MVT VT) { } ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM) - : TargetLowering(TM, TM.getObjFileLowering()) { + : TargetLowering(TM) { Subtarget = &TM.getSubtarget(); RegInfo = TM.getSubtargetImpl()->getRegisterInfo(); Itins = TM.getSubtargetImpl()->getInstrItineraryData(); diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 03791a1..7646088 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -1043,7 +1043,7 @@ HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { //===----------------------------------------------------------------------===// HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine) - : TargetLowering(targetmachine, targetmachine.getObjFileLowering()), + : TargetLowering(targetmachine), TM(targetmachine) { const HexagonSubtarget &Subtarget = TM.getSubtarget(); diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp index 216ffb1..22936dd 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -58,7 +58,7 @@ HWMultMode("msp430-hwmult-mode", cl::Hidden, clEnumValEnd)); MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM) - : TargetLowering(TM, TM.getObjFileLowering()) { + : TargetLowering(TM) { // Set up the register classes. addRegisterClass(MVT::i8, &MSP430::GR8RegClass); diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 4fb2f78..a7117ad 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -203,7 +203,7 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI) - : TargetLowering(TM, TM.getObjFileLowering()), Subtarget(STI) { + : TargetLowering(TM), Subtarget(STI) { // Mips does not have i1 type, so use i32 for // setcc operations results (slt, sgt, ...). setBooleanContents(ZeroOrOneBooleanContent); diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index 55c9737..0b0b536 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -107,7 +107,7 @@ static void ComputePTXValueVTs(const TargetLowering &TLI, Type *Ty, // NVPTXTargetLowering Constructor. NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM) - : TargetLowering(TM, TM.getObjFileLowering()), nvTM(&TM), + : TargetLowering(TM), nvTM(&TM), nvptxSubtarget(TM.getSubtarget()) { // always lower memset, memcpy, and memmove intrinsics to load/store diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 38656df..e8e4da5 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -56,7 +56,7 @@ cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden); extern cl::opt ANDIGlueBug; PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM) - : TargetLowering(TM, TM.getObjFileLowering()), + : TargetLowering(TM), Subtarget(*TM.getSubtargetImpl()) { setPow2SDivIsCheap(); diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp index 81192b70..5561bf8 100644 --- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp @@ -103,7 +103,7 @@ EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) { } AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : - TargetLowering(TM, TM.getObjFileLowering()) { + TargetLowering(TM) { Subtarget = &TM.getSubtarget(); diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index c7356cb..e6a69d2 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -1366,7 +1366,7 @@ static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { } SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) - : TargetLowering(TM, TM.getObjFileLowering()) { + : TargetLowering(TM) { Subtarget = &TM.getSubtarget(); // Set up the register classes. diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 2df3677..b282fca 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -81,7 +81,7 @@ static MachineOperand earlyUseOperand(MachineOperand Op) { } SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &tm) - : TargetLowering(tm, tm.getObjFileLowering()), + : TargetLowering(tm), Subtarget(tm.getSubtarget()) { MVT PtrVT = getPointerTy(); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 47c8ce0..92cbbe6 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -202,7 +202,7 @@ static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT, // FIXME: This should stop caching the target machine as soon as // we can remove resetOperationActions et al. X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM) - : TargetLowering(TM, TM.getObjFileLowering()) { + : TargetLowering(TM) { Subtarget = &TM.getSubtarget(); X86ScalarSSEf64 = Subtarget->hasSSE2(); X86ScalarSSEf32 = Subtarget->hasSSE1(); diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp index 5aff27b..96c43ae 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp @@ -69,7 +69,7 @@ getTargetNodeName(unsigned Opcode) const } XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM) - : TargetLowering(TM, TM.getObjFileLowering()), TM(TM), + : TargetLowering(TM), TM(TM), Subtarget(TM.getSubtarget()) { // Set up the register classes.