From: Craig Topper <craig.topper@gmail.com>
Date: Thu, 15 Aug 2013 07:30:51 +0000 (+0000)
Subject: Don't let isPermImmMask handle v16i32 since VPERMI doesn't match on that type. Remove... 
X-Git-Tag: llvmorg-3.4.0-rc1~6376
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2ffd06528dd27ba3f41be9454c701a7aee0f7424;p=platform%2Fupstream%2Fllvm.git

Don't let isPermImmMask handle v16i32 since VPERMI doesn't match on that type. Remove 128-bit vector handling from isPermImmMask too, it's covered by isPSHUFDMask.

llvm-svn: 188449
---

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 3144038d12f5..f5cb021b5d90 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -4102,41 +4102,26 @@ static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
   return (FstHalf | (SndHalf << 4));
 }
 
-// Symetric in-lane mask. Each lane has 4 elements (for imm8)
+// Symmetric in-lane mask. Each lane has 4 elements (for imm8)
 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
-  unsigned EltSize = VT.getVectorElementType().getSizeInBits();
-  if (EltSize < 32)
+  unsigned NumElts = VT.getVectorNumElements();
+  if (!(VT.is256BitVector() && NumElts == 4) &&
+      !(VT.is512BitVector() && NumElts == 8))
     return false;
 
-  unsigned NumElts = VT.getVectorNumElements();
   Imm8 = 0;
-  if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
-    for (unsigned i = 0; i != NumElts; ++i) {
-      if (Mask[i] < 0)
-        continue;
-      Imm8 |= Mask[i] << (i*2);
-    }
-    return true;
-  }
-
   unsigned LaneSize = 4;
-  SmallVector<int, 4> MaskVal(LaneSize, -1);
-
   for (unsigned l = 0; l != NumElts; l += LaneSize) {
     for (unsigned i = 0; i != LaneSize; ++i) {
       if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
         return false;
-      if (Mask[i+l] < 0)
-        continue;
-      if (MaskVal[i] < 0) {
-        MaskVal[i] = Mask[i+l] - l;
-        Imm8 |= MaskVal[i] << (i*2);
-        continue;
-      }
-      if (Mask[i+l] != (signed)(MaskVal[i]+l))
+      if (Mask[i] >= 0 && !isUndefOrEqual(Mask[i+l], Mask[i]+l))
         return false;
+      if (Mask[i+l] >= 0)
+        Imm8 |= (Mask[i+l] - l) << (i*2);
     }
   }
+
   return true;
 }
 
@@ -4165,9 +4150,7 @@ static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
       if (NumElts != 8 || l == 0)
         continue;
       // VPERMILPS handling
-      if (Mask[i] < 0)
-        continue;
-      if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
+      if (Mask[i] >= 0 && !isUndefOrEqual(Mask[i+l], Mask[i]+l))
         return false;
     }
   }
diff --git a/llvm/test/CodeGen/X86/avx512-shuffle.ll b/llvm/test/CodeGen/X86/avx512-shuffle.ll
index 9f3d86a5e646..71e7ebc1848c 100644
--- a/llvm/test/CodeGen/X86/avx512-shuffle.ll
+++ b/llvm/test/CodeGen/X86/avx512-shuffle.ll
@@ -32,6 +32,14 @@ define <16 x i32> @test2(<16 x i32> %a) nounwind {
   ret <16 x i32> %c
 }
 
+; CHECK: test2b:
+; CHECK: vpermd
+; CHECK: ret
+define <16 x i32> @test2b(<16 x i32> %a) nounwind {
+  %c = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
+  ret <16 x i32> %c
+}
+
 ; CHECK: test3:
 ; CHECK: vpermq
 ; CHECK: ret