From: Eric Anholt <eric@anholt.net>
Date: Mon, 26 Nov 2012 21:39:11 +0000 (-0800)
Subject: i965/fp: Fix segfault on gen4 TXB instructions.
X-Git-Tag: mesa-9.1-rc1~1075
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2f7915bdb9e1f12861cddbb97f8101693565a59e;p=platform%2Fupstream%2Fmesa.git

i965/fp: Fix segfault on gen4 TXB instructions.

The gen4 simd16 workaround looks at ir->type to determine how much
storage to allocate for the simd16 value.  In fragment programs,
texturing only ever returns float vec4s (unlike GLSL, which can also
have scalar floats or vector integers), so this is the right type.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56962
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
---

diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
index bb8cd9a..4be7779 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
@@ -441,6 +441,8 @@ fs_visitor::emit_fragment_program_code()
             break;
          }
 
+         ir->type = glsl_type::vec4_type;
+
          const glsl_type *coordinate_type;
          switch (fpi->TexSrcTarget) {
          case TEXTURE_1D_INDEX: