From: Colin LeMahieu Date: Fri, 16 Jan 2015 17:05:27 +0000 (+0000) Subject: [Hexagon] Updating call/jump instruction patterns. X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2e3a26de0ce02ee85fa3b7a26d2d1a7afc5a3a36;p=platform%2Fupstream%2Fllvm.git [Hexagon] Updating call/jump instruction patterns. llvm-svn: 226288 --- diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index ecf4c79..61e0f72 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -404,6 +404,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, bool &isTailCall = CLI.IsTailCall; CallingConv::ID CallConv = CLI.CallConv; bool isVarArg = CLI.IsVarArg; + bool doesNotReturn = CLI.DoesNotReturn; bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); @@ -597,7 +598,8 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (isTailCall) return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops); - Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops); + int OpCode = doesNotReturn ? HexagonISD::CALLv3nr : HexagonISD::CALLv3; + Chain = DAG.getNode(OpCode, dl, NodeTys, Ops); InFlag = Chain.getValue(1); // Create the CALLSEQ_END node. @@ -1487,7 +1489,9 @@ HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { case HexagonISD::Lo: return "HexagonISD::Lo"; case HexagonISD::FTOI: return "HexagonISD::FTOI"; case HexagonISD::ITOF: return "HexagonISD::ITOF"; - case HexagonISD::CALL: return "HexagonISD::CALL"; + case HexagonISD::CALLv3: return "HexagonISD::CALLv3"; + case HexagonISD::CALLv3nr: return "HexagonISD::CALLv3nr"; + case HexagonISD::CALLR: return "HexagonISD::CALLR"; case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG"; case HexagonISD::BR_JT: return "HexagonISD::BR_JT"; case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN"; diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index d03b1b8..822a191 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -49,7 +49,10 @@ bool isPositiveHalfWord(SDNode *N); FTOI, // FP to Int within a FP register. ITOF, // Int to FP within a FP register. - CALL, // A call instruction. + CALLv3, // A V3+ call instruction. + CALLv3nr, // A V3+ call instruction that doesn't return. + CALLR, + RET_FLAG, // Return with a flag operand. BR_JT, // Jump table. BARRIER, // Memory barrier diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 3c7abfc..ed908e4 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -3927,11 +3927,10 @@ def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1), // Support for generating global address. // Taken from X86InstrInfo.td. -def SDTHexagonCONST32 : SDTypeProfile<1, 1, [ - SDTCisVT<0, i32>, - SDTCisVT<1, i32>, - SDTCisPtrTy<0>]>; -def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>; +def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, + SDTCisVT<1, i32>, + SDTCisPtrTy<0>]>; +def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>; def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>; // HI/LO Instructions @@ -4028,29 +4027,17 @@ def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins), "$dst = xor($dst, $dst)", [(set (i1 PredRegs:$dst), 0)]>; -def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), - "$dst = mpy($src1, $src2)", - [(set (i32 IntRegs:$dst), - (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))), - (i64 (sext (i32 IntRegs:$src2))))), - (i32 32)))))]>; - // Pseudo instructions. def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; - -def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, +def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; -def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, - [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; - def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, [SDNPHasChain, SDNPOutGlue]>; +def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; -def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; - -def call : SDNode<"HexagonISD::CALL", SDT_SPCall, - [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; +def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain, // Optional Flag and Variable Arguments. @@ -4094,13 +4081,6 @@ isTerminator = 1, isCodeGenOnly = 1 in { [], "", J_tc_2early_SLOT23>; } -// Map call instruction. -def : Pat<(call (i32 IntRegs:$dst)), - (J2_callr (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>; -def : Pat<(call tglobaladdr:$dst), - (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>; -def : Pat<(call texternalsym:$dst), - (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>; //Tail calls. def : Pat<(HexagonTCRet tglobaladdr:$dst), (TCRETURNtg tglobaladdr:$dst)>; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td index 8e91476..76d4d83 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td @@ -67,6 +67,9 @@ multiclass T_Calls { let isCodeGenOnly = 0 in defm J2_call: T_Calls<"">, PredRel; +let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs in +def CALLv3nr : T_Call<"">, PredRel; + //===----------------------------------------------------------------------===// // J - //===----------------------------------------------------------------------===// @@ -76,13 +79,11 @@ defm J2_call: T_Calls<"">, PredRel; // JR + //===----------------------------------------------------------------------===// // Call subroutine from register. -let isCall = 1, hasSideEffects = 0, - Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31, - P0, P1, P2, P3, LC0, LC1, SA0, SA1] in { - def CALLRv3 : JRInst<(outs), (ins IntRegs:$dst), - "callr $dst", - []>, Requires<[HasV3TOnly]>; - } + +let isCodeGenOnly = 1, Defs = VolatileV3.Regs, validSubTargets = HasV3SubT in { + def CALLRv3nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return. +} + //===----------------------------------------------------------------------===// // JR - @@ -178,11 +179,19 @@ let AddedComplexity = 200 in { //def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset), // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>; - // Map call instruction -def : Pat<(call (i32 IntRegs:$dst)), - (J2_call (i32 IntRegs:$dst))>, Requires<[HasV3T]>; -def : Pat<(call tglobaladdr:$dst), +def : Pat<(callv3 (i32 IntRegs:$dst)), + (J2_callr (i32 IntRegs:$dst))>, Requires<[HasV3T]>; +def : Pat<(callv3 tglobaladdr:$dst), (J2_call tglobaladdr:$dst)>, Requires<[HasV3T]>; -def : Pat<(call texternalsym:$dst), +def : Pat<(callv3 texternalsym:$dst), (J2_call texternalsym:$dst)>, Requires<[HasV3T]>; +def : Pat<(callv3 tglobaltlsaddr:$dst), + (J2_call tglobaltlsaddr:$dst)>, Requires<[HasV3T]>; + +def : Pat<(callv3nr (i32 IntRegs:$dst)), + (CALLRv3nr (i32 IntRegs:$dst))>, Requires<[HasV3T]>; +def : Pat<(callv3nr tglobaladdr:$dst), + (CALLv3nr tglobaladdr:$dst)>, Requires<[HasV3T]>; +def : Pat<(callv3nr texternalsym:$dst), + (CALLv3nr texternalsym:$dst)>, Requires<[HasV3T]>; diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index c960527..50cefcc 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -264,8 +264,7 @@ bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) { static bool IsIndirectCall(MachineInstr* MI) { - return ((MI->getOpcode() == Hexagon::J2_callr) || - (MI->getOpcode() == Hexagon::CALLRv3)); + return MI->getOpcode() == Hexagon::J2_callr; } // Reserve resources for constant extender. Trigure an assertion if