From: David Woodhouse <David.Woodhouse@intel.com>
Date: Tue, 15 Jun 2010 09:57:57 +0000 (+0100)
Subject: intel-iommu: Force-disable IOMMU for iGFX on broken Cantiga revisions.
X-Git-Tag: v2.6.35-rc4~64^2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2d9e667efdfb4e986074d98e7d9a424003c7c43b;p=platform%2Fkernel%2Flinux-3.10.git

intel-iommu: Force-disable IOMMU for iGFX on broken Cantiga revisions.

Certain revisions of this chipset appear to be broken. There is a shadow
GTT which mirrors the real GTT but contains pre-translated physical
addresses, for performance reasons. When a GTT update happens, the
translations are done once and the resulting physical addresses written
back to the shadow GTT.

Except sometimes, the physical address is actually written back to the
_real_ GTT, not the shadow GTT. Thus we start to see faults when that
physical address is fed through translation again.

Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
---

diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c
index bf8fd91..c9171be 100644
--- a/drivers/pci/intel-iommu.c
+++ b/drivers/pci/intel-iommu.c
@@ -340,7 +340,7 @@ int dmar_disabled = 0;
 int dmar_disabled = 1;
 #endif /*CONFIG_DMAR_DEFAULT_ON*/
 
-static int __initdata dmar_map_gfx = 1;
+static int dmar_map_gfx = 1;
 static int dmar_forcedac;
 static int intel_iommu_strict;
 
@@ -3721,6 +3721,12 @@ static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
 	 */
 	printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
 	rwbf_quirk = 1;
+
+	/* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */
+	if (dev->revision == 0x07) {
+		printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
+		dmar_map_gfx = 0;
+	}
 }
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);