From: SooChan Lim <sc1.lim@samsung.com>
Date: Mon, 6 Mar 2017 06:19:20 +0000 (+0900)
Subject: fix the typo
X-Git-Tag: accepted/tizen/common/20170324.123559~5
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2d94e4abd4a94ce7701ea173ff96f6fea5659a7d;p=platform%2Fadaptation%2Fsamsung_exynos%2Flibtbm-exynos.git

fix the typo

Change-Id: I28f04fdd34403c0d5b7a3c318b3dc2ea4e54e553
---

diff --git a/configure.ac b/configure.ac
index 13b73f9..99ca441 100644
--- a/configure.ac
+++ b/configure.ac
@@ -48,7 +48,7 @@ AC_ARG_ENABLE(cachectrl,
 	      [CACHE_CTRL=$enableval], [CACHE_CTRL=yes])
 
 if test "x$CACHE_CTRL" = xyes; then
-    AC_DEFINE(ENABLE_CACHECRTL, 1, [Enable cache control])
+    AC_DEFINE(ENABLE_CACHECTRL, 1, [Enable cache control])
 fi
 
 AC_ARG_ENABLE(backendctrl,
diff --git a/src/tbm_bufmgr_exynos.c b/src/tbm_bufmgr_exynos.c
index a057a0e..86fad59 100644
--- a/src/tbm_bufmgr_exynos.c
+++ b/src/tbm_bufmgr_exynos.c
@@ -272,7 +272,7 @@ uint32_t tbm_exynos_color_format_list[TBM_COLOR_FORMAT_COUNT] = {
 										TBM_FORMAT_YUV420
 									};
 
-#ifdef ENABLE_CACHECRTL
+#ifdef ENABLE_CACHECTRL
 #ifdef TGL_GET_VERSION
 static inline int
 _tgl_get_version(int fd)
@@ -469,7 +469,7 @@ _exynos_cache_flush(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, in
 static int
 _bo_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, int import)
 {
-#ifdef ENABLE_CACHECRTL
+#ifdef ENABLE_CACHECTRL
 	EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0);
 	EXYNOS_RETURN_VAL_IF_FAIL(bo_exynos != NULL, 0);
 
@@ -495,7 +495,7 @@ _bo_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, i
 static int
 _bo_set_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, int device, int opt)
 {
-#ifdef ENABLE_CACHECRTL
+#ifdef ENABLE_CACHECTRL
 	EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0);
 	EXYNOS_RETURN_VAL_IF_FAIL(bo_exynos != NULL, 0);
 
@@ -562,7 +562,7 @@ _bo_set_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, in
 static int
 _bo_save_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos)
 {
-#ifdef ENABLE_CACHECRTL
+#ifdef ENABLE_CACHECTRL
 	EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0);
 	EXYNOS_RETURN_VAL_IF_FAIL(bo_exynos != NULL, 0);
 
@@ -586,7 +586,7 @@ _bo_save_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos)
 static void
 _bo_destroy_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos)
 {
-#ifdef ENABLE_CACHECRTL
+#ifdef ENABLE_CACHECTRL
 	EXYNOS_RETURN_IF_FAIL(bufmgr_exynos != NULL);
 	EXYNOS_RETURN_IF_FAIL(bo_exynos != NULL);
 
@@ -600,7 +600,7 @@ _bo_destroy_cache_state(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos
 static int
 _bufmgr_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos)
 {
-#ifdef ENABLE_CACHECRTL
+#ifdef ENABLE_CACHECTRL
 	EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0);
 
 	if (bufmgr_exynos->use_dma_fence)
@@ -639,7 +639,7 @@ _bufmgr_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos)
 static void
 _bufmgr_deinit_cache_state(tbm_bufmgr_exynos bufmgr_exynos)
 {
-#ifdef ENABLE_CACHECRTL
+#ifdef ENABLE_CACHECTRL
 	EXYNOS_RETURN_IF_FAIL(bufmgr_exynos != NULL);
 
 	if (bufmgr_exynos->use_dma_fence)
@@ -1536,7 +1536,7 @@ tbm_exynos_bo_unmap(tbm_bo bo)
 	if (bo_exynos->map_cnt == 0)
 		_bo_save_cache_state(bufmgr_exynos, bo_exynos);
 
-#ifdef ENABLE_CACHECRTL
+#ifdef ENABLE_CACHECTRL
 	if (bo_exynos->last_map_device == TBM_DEVICE_CPU)
 		_exynos_cache_flush(bufmgr_exynos, bo_exynos, TBM_EXYNOS_CACHE_FLUSH_ALL);
 #endif
diff --git a/src/tbm_bufmgr_tgl.h b/src/tbm_bufmgr_tgl.h
index f9cbd6f..0ad453c 100644
--- a/src/tbm_bufmgr_tgl.h
+++ b/src/tbm_bufmgr_tgl.h
@@ -34,7 +34,7 @@
 
 #include <linux/ioctl.h>
 
-#ifdef ENABLE_CACHECRTL
+#ifdef ENABLE_CACHECTRL
 static char tgl_devfile[] = "/dev/slp_global_lock";
 static char tgl_devfile1[] = "/dev/tgl";
 #endif
@@ -125,7 +125,7 @@ enum {
 /* get user data with key */
 #define TGL_IOCTL_GET_DATA		TGL_IOR(_TGL_GET_DATA, struct tgl_usr_data)
 
-#ifdef ENABLE_CACHECRTL
+#ifdef ENABLE_CACHECTRL
 /* indicate cache units. */
 enum e_drm_exynos_gem_cache_sel {
 	EXYNOS_DRM_L1_CACHE		= 1 << 0,