From: Konrad Dybcio Date: Tue, 26 Sep 2023 18:24:36 +0000 (+0200) Subject: drm/msm/a6xx: Fix unknown speedbin case X-Git-Tag: v6.6.17~3388 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2d70a9002ed3cb449ff003405d51c8d6a42c1554;p=platform%2Fkernel%2Flinux-rpi.git drm/msm/a6xx: Fix unknown speedbin case [ Upstream commit 75cb60d4f5f762b12643b67cbefefcf05ecfd7eb ] When opp-supported-hw is present under an OPP node, but no form of opp_set_supported_hw() has been called, that OPP is ignored by the API and marked as unsupported. Before Commit c928a05e4415 ("drm/msm/adreno: Move speedbin mapping to device table"), an unknown speedbin would result in marking all OPPs as available, but it's better to avoid potentially overclocking the silicon - the GMU will simply refuse to power up the chip. Currently, the Adreno speedbin code does just that (AND returns an invalid error, (int)UINT_MAX). Fix that by defaulting to speedbin 0 (which is conveniently always bound to fuseval == 0). Fixes: c928a05e4415 ("drm/msm/adreno: Move speedbin mapping to device table") Signed-off-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/559604/ Signed-off-by: Rob Clark Signed-off-by: Sasha Levin --- diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index d4e85e2..522ca7f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2237,7 +2237,7 @@ static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *i DRM_DEV_ERROR(dev, "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", speedbin); - return UINT_MAX; + supp_hw = BIT(0); /* Default */ } ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);