From: Elena Demikhovsky Date: Tue, 29 Mar 2016 06:55:56 +0000 (+0000) Subject: Added 2 notes X-Git-Tag: llvmorg-3.9.0-rc1~10653 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2c35e20dd7f2874314a8f59cd7865a67fb5d1e2c;p=platform%2Fupstream%2Fllvm.git Added 2 notes 1) Skylake and KNL support for X86 2) masked intrinsics load/store/gather/scatter Differential Revision: http://reviews.llvm.org/D18353 llvm-svn: 264703 --- diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 982ade9..14fc126 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -71,6 +71,13 @@ Non-comprehensive list of changes in this release Makes programs 10x faster by doing Special New Thing. +Changes to the LLVM IR +---------------------- + +* New intrinsics ``llvm.masked.load``, ``llvm.masked.store``, + ``llvm.masked.gather`` and ``llvm.masked.scatter`` were introduced to the + LLVM IR to allow selective memory access for vector data types. + Changes to the ARM Backend -------------------------- @@ -90,9 +97,15 @@ Changes to the PowerPC Target Changes to the X86 Target ------------------------------ +------------------------- - During this release ... +* LLVM now supports the Intel CPU codenamed Skylake Server with AVX-512 + extensions using ``-march=skylake-avx512``. The switch enables the + ISA extensions AVX-512{F, CD, VL, BW, DQ}. + +* LLVM now supports the Intel CPU codenamed Knights Landing with AVX-512 + extensions using ``-march=knl``. The switch enables the ISA extensions + AVX-512{F, CD, ER, PF}. Changes to the AMDGPU Target -----------------------------