From: Stephen M. Cameron Date: Tue, 1 May 2012 16:42:30 +0000 (-0500) Subject: [SCSI] hpsa: do not read from controller unnecessarily in completion code X-Git-Tag: v3.12-rc1~3176^2~43 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2c17d2da8c9ef2c5be5077d3995041791e38094d;p=kernel%2Fkernel-generic.git [SCSI] hpsa: do not read from controller unnecessarily in completion code MSI/MSI-X interrupts can't race the DMA completion they are communicating so no need to read from controller to flush the DMA to the host if MSI or MSI-X interrupts are being used. Signed-off-by: Stephen M. Cameron Signed-off-by: James Bottomley --- diff --git a/drivers/scsi/hpsa.h b/drivers/scsi/hpsa.h index 7b28d54..48f7812 100644 --- a/drivers/scsi/hpsa.h +++ b/drivers/scsi/hpsa.h @@ -258,12 +258,12 @@ static unsigned long SA5_performant_completed(struct ctlr_info *h) { unsigned long register_value = FIFO_EMPTY; - /* flush the controller write of the reply queue by reading - * outbound doorbell status register. - */ - register_value = readl(h->vaddr + SA5_OUTDB_STATUS); /* msi auto clears the interrupt pending bit. */ if (!(h->msi_vector || h->msix_vector)) { + /* flush the controller write of the reply queue by reading + * outbound doorbell status register. + */ + register_value = readl(h->vaddr + SA5_OUTDB_STATUS); writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); /* Do a read in order to flush the write to the controller * (as per spec.)