From: Marek Vasut <marex@denx.de>
Date: Tue, 19 Feb 2019 00:11:24 +0000 (+0100)
Subject: ARM: socfpga: Configure PL310 latencies
X-Git-Tag: v2019.04-rc3~5^2~1
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2c0b300bc30881c09519d1f7bfa46a04b0d6d1d5;p=platform%2Fkernel%2Fu-boot.git

ARM: socfpga: Configure PL310 latencies

Configure the PL310 tag and data latency registers, which slightly
improves performance and aligns the behavior with Linux.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
---

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index e1adea1..fcf211d 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -62,6 +62,9 @@ void v7_outer_cache_enable(void)
 	/* Disable the L2 cache */
 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 
+	writel(0x111, &pl310->pl310_tag_latency_ctrl);
+	writel(0x121, &pl310->pl310_data_latency_ctrl);
+
 	/* enable BRESP, instruction and data prefetch, full line of zeroes */
 	setbits_le32(&pl310->pl310_aux_ctrl,
 		     L310_AUX_CTRL_DATA_PREFETCH_MASK |