From: Minkyu Kang Date: Mon, 3 Jan 2011 07:02:17 +0000 (+0900) Subject: s5p: universal: don't use r8 X-Git-Tag: v0.2~95 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2bf8c4819492884dca5b698c440eea26f912e1d2;p=kernel%2Fu-boot.git s5p: universal: don't use r8 r8 is fixed by pointer of gd. (declared at global_data.h) Signed-off-by: Minkyu Kang --- diff --git a/board/samsung/universal_c110/lowlevel_init.S b/board/samsung/universal_c110/lowlevel_init.S index d77395e..9e4ef1f 100644 --- a/board/samsung/universal_c110/lowlevel_init.S +++ b/board/samsung/universal_c110/lowlevel_init.S @@ -37,13 +37,10 @@ * * r5 has zero always * r7 has S5PC100 GPIO base, 0xE0300000 - * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively + * r6 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on */ -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init lowlevel_init: mov r11, lr @@ -52,7 +49,7 @@ lowlevel_init: mov r5, #0 ldr r7, =S5PC100_GPIO_BASE - ldr r8, =S5PC100_GPIO_BASE + ldr r6, =S5PC100_GPIO_BASE /* Read CPU ID */ ldr r2, =S5PC100_PRO_ID ldr r0, [r2] @@ -60,10 +57,10 @@ lowlevel_init: and r0, r0, r1 cmp r0, r5 beq 100f - ldr r8, =S5PC110_GPIO_BASE + ldr r6, =S5PC110_GPIO_BASE 100: /* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */ - cmp r7, r8 + cmp r7, r6 beq skip_check_didle @Support C110 only ldr r0, =S5PC110_RST_STAT @@ -71,12 +68,12 @@ lowlevel_init: and r1, r1, #S5PC110_RST_STAT_WAKEUP_MODE_MASK cmp r1, #S5PC110_DEEPIDLE_WAKEUP beq didle_wakeup - cmp r7, r8 + cmp r7, r6 skip_check_didle: #ifndef DEBUG_PM_C110 - addeq r0, r8, #0x280 @S5PC100_GPIO_J4_OFFSET - addne r0, r8, #0x2C0 @S5PC110_GPIO_J4_OFFSET + addeq r0, r6, #0x280 @S5PC100_GPIO_J4_OFFSET + addne r0, r6, #0x2C0 @S5PC110_GPIO_J4_OFFSET ldr r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET bic r1, r1, #(0xf << 4) @ 1 * 4-bit orr r1, r1, #(0x1 << 4) @@ -243,7 +240,7 @@ skip_check_didle: * HF[2] : High Frequency Enable (Over 66MHz) * WM[1] : Sync Write */ - cmp r7, r8 + cmp r7, r6 ldrne r1, =0xE006 ldrne r0, =0xB001E442 strneh r1, [r0] @@ -259,7 +256,7 @@ skip_check_didle: strne r1, [r0, #0x108] /* Board detection to set proper memory configuration */ - cmp r7, r8 + cmp r7, r6 moveq r9, #1 /* r9 has 1Gib default at s5pc100 */ movne r9, #2 /* r9 has 2Gib default at s5pc110 */ @@ -328,14 +325,14 @@ skip_check_didle: bne 1f wakeup: #ifdef DEBUG_PM_C110 - mov r0, r8 + mov r0, r6 ldr r1, =0x22222222 str r1, [r0, #0x0] @S5PC100_GPIO_A0_OFFSET ldr r1, =0x00002222 str r1, [r0, #0x20] @S5PC100_GPIO_A1_OFFSET /* UART_SEL MP0_5[7] at S5PC110 */ - add r0, r8, #0x360 @S5PC110_GPIO_MP0_5_OFFSET + add r0, r6, #0x360 @S5PC110_GPIO_MP0_5_OFFSET ldr r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit orr r1, r1, #(0x1 << 28) @ Output @@ -372,7 +369,7 @@ wakeup: /* turn off L2 cache */ bl l2_cache_disable - cmp r7, r8 + cmp r7, r6 ldreq r0, =0xC100 ldrne r0, =0xC110 @@ -382,7 +379,7 @@ wakeup: /* turn on L2 cache */ bl l2_cache_enable - cmp r7, r8 + cmp r7, r6 /* Load return address and jump to kernel */ ldreq r0, =S5PC100_INFORM0 ldrne r0, =S5PC110_INFORM0 @@ -395,7 +392,7 @@ wakeup: nop nop #else - cmp r7, r8 + cmp r7, r6 /* Clear wakeup status register */ ldreq r0, =S5PC100_WAKEUP_STAT ldrne r0, =S5PC110_WAKEUP_STAT @@ -445,7 +442,7 @@ system_clock_init: ldr r0, =S5PC100_CLOCK_BASE @ 0xE0100000 /* Check S5PC100 */ - cmp r7, r8 + cmp r7, r6 bne 110f 100: #ifndef DEBUG_PM_C110 @@ -625,19 +622,19 @@ internal_ram_init: */ uart_asm_init: /* set GPIO to enable UART0-UART4 */ - mov r0, r8 + mov r0, r6 ldr r1, =0x22222222 str r1, [r0, #0x0] @S5PC100_GPIO_A0_OFFSET ldr r1, =0x00002222 str r1, [r0, #0x20] @S5PC100_GPIO_A1_OFFSET /* Check S5PC100 */ - cmp r7, r8 + cmp r7, r6 bne 110f #ifndef DEBUG_PM_C110 /* UART_SEL GPK0[5] at S5PC100 */ - add r0, r8, #0x2A0 @S5PC100_GPIO_K0_OFFSET + add r0, r6, #0x2A0 @S5PC100_GPIO_K0_OFFSET ldr r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit orr r1, r1, #(0x1 << 20) @ Output @@ -659,7 +656,7 @@ uart_asm_init: * 0xE020'0360 is reserved address at S5PC100 */ /* UART_SEL MP0_5[7] at S5PC110 */ - add r0, r8, #0x360 @S5PC110_GPIO_MP0_5_OFFSET + add r0, r6, #0x360 @S5PC110_GPIO_MP0_5_OFFSET ldr r1, [r0, #0x0] @S5PC1XX_GPIO_CON_OFFSET bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit orr r1, r1, #(0x1 << 28) @ Output diff --git a/board/samsung/universal_c210/lowlevel_init.S b/board/samsung/universal_c210/lowlevel_init.S index 17e2d2f..38b37d6 100644 --- a/board/samsung/universal_c210/lowlevel_init.S +++ b/board/samsung/universal_c210/lowlevel_init.S @@ -33,14 +33,10 @@ * Register usages: * * r5 has zero always - * r6 is used at memory configuration * r7 has GPIO part1 base 0x11400000 - * r8 has GPIO part2 base 0x11000000 + * r6 has GPIO part2 base 0x11000000 */ -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - .globl lowlevel_init lowlevel_init: mov r11, lr @@ -49,7 +45,7 @@ lowlevel_init: mov r5, #0 ldr r7, =S5PC210_GPIO_PART1_BASE - ldr r8, =S5PC210_GPIO_PART2_BASE + ldr r6, =S5PC210_GPIO_PART2_BASE /* System Timer */ ldr r0, =S5PC210_SYSTIMER_BASE @@ -63,7 +59,7 @@ lowlevel_init: #ifndef CONFIG_PRELOADER /* Workaround: PMIC manual reset */ /* nPOWER: XEINT_23: GPX2[7] */ - add r0, r8, #0xC40 @ S5PC210_GPIO_X2_OFFSET + add r0, r6, #0xC40 @ S5PC210_GPIO_X2_OFFSET ldr r1, [r0, #0x0] bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit orr r1, r1, #(0x1 << 28) @ Output @@ -203,7 +199,7 @@ uart_asm_init: str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET /* UART_SEL GPY4[7] (part2) at S5PC210 */ - add r0, r8, #0x1A0 @ S5PC210_GPIO_Y4_OFFSET + add r0, r6, #0x1A0 @ S5PC210_GPIO_Y4_OFFSET ldr r1, [r0, #0x0] bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit orr r1, r1, #(0x1 << 28)