From: Homer Hsing <homer.xing@intel.com>
Date: Wed, 7 Aug 2013 04:19:53 +0000 (+0800)
Subject: support 64bit-integer AND(&), OR(|), XOR(^) arithmetic
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2b6433393ceac1eb9fda432ea5a604270cd8b657;p=contrib%2Fbeignet.git

support 64bit-integer AND(&), OR(|), XOR(^) arithmetic

v3: folded similar code into a "for-loop"

Signed-off-by: Homer Hsing <homer.xing@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
---

diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index ff13302..0c29beb 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -162,6 +162,63 @@ namespace gbe
       case SEL_OP_AND:  p->AND(dst, src0, src1); break;
       case SEL_OP_OR:   p->OR (dst, src0, src1);  break;
       case SEL_OP_XOR:  p->XOR(dst, src0, src1); break;
+      case SEL_OP_I64AND:
+        {
+          GenRegister xdst = GenRegister::retype(dst, GEN_TYPE_UL),
+                      xsrc0 = GenRegister::retype(src0, GEN_TYPE_UL),
+                      xsrc1 = GenRegister::retype(src1, GEN_TYPE_UL);
+          int execWidth = p->curr.execWidth;
+          p->push();
+          p->curr.execWidth = 8;
+          for (int nib = 0; nib < execWidth / 4; nib ++) {
+            p->curr.chooseNib(nib);
+            p->AND(xdst.bottom_half(), xsrc0.bottom_half(), xsrc1.bottom_half());
+            p->AND(xdst.top_half(), xsrc0.top_half(), xsrc1.top_half());
+            xdst = GenRegister::suboffset(xdst, 4),
+            xsrc0 = GenRegister::suboffset(xsrc0, 4),
+            xsrc1 = GenRegister::suboffset(xsrc1, 4);
+          }
+          p->pop();
+        }
+        break;
+      case SEL_OP_I64OR:
+        {
+          GenRegister xdst = GenRegister::retype(dst, GEN_TYPE_UL),
+                      xsrc0 = GenRegister::retype(src0, GEN_TYPE_UL),
+                      xsrc1 = GenRegister::retype(src1, GEN_TYPE_UL);
+          int execWidth = p->curr.execWidth;
+          p->push();
+          p->curr.execWidth = 8;
+          for (int nib = 0; nib < execWidth / 4; nib ++) {
+            p->curr.chooseNib(nib);
+            p->OR(xdst.bottom_half(), xsrc0.bottom_half(), xsrc1.bottom_half());
+            p->OR(xdst.top_half(), xsrc0.top_half(), xsrc1.top_half());
+            xdst = GenRegister::suboffset(xdst, 4),
+            xsrc0 = GenRegister::suboffset(xsrc0, 4),
+            xsrc1 = GenRegister::suboffset(xsrc1, 4);
+          }
+          p->pop();
+        }
+        break;
+      case SEL_OP_I64XOR:
+        {
+          GenRegister xdst = GenRegister::retype(dst, GEN_TYPE_UL),
+                      xsrc0 = GenRegister::retype(src0, GEN_TYPE_UL),
+                      xsrc1 = GenRegister::retype(src1, GEN_TYPE_UL);
+          int execWidth = p->curr.execWidth;
+          p->push();
+          p->curr.execWidth = 8;
+          for (int nib = 0; nib < execWidth / 4; nib ++) {
+            p->curr.chooseNib(nib);
+            p->XOR(xdst.bottom_half(), xsrc0.bottom_half(), xsrc1.bottom_half());
+            p->XOR(xdst.top_half(), xsrc0.top_half(), xsrc1.top_half());
+            xdst = GenRegister::suboffset(xdst, 4),
+            xsrc0 = GenRegister::suboffset(xsrc0, 4),
+            xsrc1 = GenRegister::suboffset(xsrc1, 4);
+          }
+          p->pop();
+        }
+        break;
       case SEL_OP_SHR:  p->SHR(dst, src0, src1); break;
       case SEL_OP_SHL:  p->SHL(dst, src0, src1); break;
       case SEL_OP_RSR:  p->RSR(dst, src0, src1); break;
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 66cfa31..7e9402d 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -423,6 +423,9 @@ namespace gbe
     ALU2(AND)
     ALU2(OR)
     ALU2(XOR)
+    ALU2(I64AND)
+    ALU2(I64OR)
+    ALU2(I64XOR)
     ALU2(SHR)
     ALU2(SHL)
     ALU2(RSR)
@@ -1434,9 +1437,24 @@ namespace gbe
             sel.ADD(dst, src0, src1);
           sel.pop();
           break;
-        case OP_XOR: sel.XOR(dst, src0, src1); break;
-        case OP_OR:  sel.OR(dst, src0,  src1); break;
-        case OP_AND: sel.AND(dst, src0, src1); break;
+        case OP_XOR:
+          if (type == Type::TYPE_U64 || type == Type::TYPE_S64)
+            sel.I64XOR(dst, src0, src1);
+          else
+            sel.XOR(dst, src0, src1);
+          break;
+        case OP_OR:
+          if (type == Type::TYPE_U64 || type == Type::TYPE_S64)
+            sel.I64OR(dst, src0, src1);
+          else
+            sel.OR(dst, src0, src1);
+          break;
+        case OP_AND:
+          if (type == Type::TYPE_U64 || type == Type::TYPE_S64)
+            sel.I64AND(dst, src0, src1);
+          else
+            sel.AND(dst, src0, src1);
+          break;
         case OP_SUB:
           if (type == Type::TYPE_U64 || type == Type::TYPE_S64) {
             GenRegister t = sel.selReg(sel.reg(RegisterFamily::FAMILY_QWORD), Type::TYPE_S64);
diff --git a/backend/src/backend/gen_insn_selection.hxx b/backend/src/backend/gen_insn_selection.hxx
index 8eeb19f..7664c8f 100644
--- a/backend/src/backend/gen_insn_selection.hxx
+++ b/backend/src/backend/gen_insn_selection.hxx
@@ -14,6 +14,9 @@ DECL_SELECTION_IR(SEL, BinaryInstruction)
 DECL_SELECTION_IR(AND, BinaryInstruction)
 DECL_SELECTION_IR(OR, BinaryInstruction)
 DECL_SELECTION_IR(XOR, BinaryInstruction)
+DECL_SELECTION_IR(I64AND, BinaryInstruction)
+DECL_SELECTION_IR(I64OR, BinaryInstruction)
+DECL_SELECTION_IR(I64XOR, BinaryInstruction)
 DECL_SELECTION_IR(SHR, BinaryInstruction)
 DECL_SELECTION_IR(SHL, BinaryInstruction)
 DECL_SELECTION_IR(RSR, BinaryInstruction)
diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp
index 3de87d4..45095db 100644
--- a/backend/src/ir/instruction.cpp
+++ b/backend/src/ir/instruction.cpp
@@ -672,6 +672,7 @@ namespace ir {
     static const Type logicalType[] = {TYPE_S8,  TYPE_U8,
                                        TYPE_S16, TYPE_U16,
                                        TYPE_S32, TYPE_U32,
+                                       TYPE_S64, TYPE_U64,
                                        TYPE_BOOL};
     static const uint32_t logicalTypeNum = ARRAY_ELEM_NUM(logicalType);