From: Nanley Chery <nanley.g.chery@intel.com>
Date: Mon, 21 Nov 2022 21:37:30 +0000 (-0800)
Subject: intel: Hook up RENDER_SURFACE_STATE::DecompressInL3
X-Git-Tag: upstream/23.3.3~15581
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2add57d0c22b4aa0e85ca1280c15b4350d1c7c03;p=platform%2Fupstream%2Fmesa.git

intel: Hook up RENDER_SURFACE_STATE::DecompressInL3

The sampler's decompressor seems to lack support for some types of
format re-interpretation. Use the more capable decompressor for these
cases. This will be needed to avoid regressing piglit's
arb_texture_view-rendering-formats in later commits.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19937>
---

diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml
index c4ff096..c4c0b99 100644
--- a/src/intel/genxml/gen12.xml
+++ b/src/intel/genxml/gen12.xml
@@ -731,6 +731,7 @@
       <value name="180DEG" value="2" />
       <value name="270DEG" value="3" />
     </field>
+    <field name="Decompress In L3" start="159" end="159" type="bool" />
     <field name="MIP Count / LOD" start="160" end="163" type="uint" />
     <field name="Surface Min LOD" start="164" end="167" type="uint" />
     <field name="Mip Tail Start LOD" start="168" end="171" type="uint" />
diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index ff9e14a..72c076f 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -774,6 +774,7 @@
       <value name="180DEG" value="2" />
       <value name="270DEG" value="3" />
     </field>
+    <field name="Decompress In L3" start="159" end="159" type="bool" />
     <field name="MIP Count / LOD" start="160" end="163" type="uint" />
     <field name="Surface Min LOD" start="164" end="167" type="uint" />
     <field name="Mip Tail Start LOD" start="168" end="171" type="uint" />
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index 59158f8..455e2f3 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -643,6 +643,20 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 #endif
 #if GFX_VER >= 12
       s.MemoryCompressionEnable = info->aux_usage == ISL_AUX_USAGE_MC;
+
+      /* The Tiger Lake PRM for RENDER_SURFACE_STATE::DecompressInL3 says:
+       *
+       *    When this field is set to 1h, the associated compressible surface,
+       *    when accessed by sampler and data-port, will be uncompressed in
+       *    L3. If the surface is not compressible, this bit field is ignored.
+       *
+       * The sampler's decompressor seems to lack support for some types of
+       * format re-interpretation. Use the more capable decompressor for these
+       * cases.
+       */
+      s.DecompressInL3 =
+         !isl_formats_have_same_bits_per_channel(info->surf->format,
+                                                 info->view->format);
 #endif
 #if GFX_VER >= 9
       /* Some CCS aux usages have format restrictions. The Skylake PRM doc for