From: Ahmed Bougacha Date: Tue, 16 Aug 2016 14:02:47 +0000 (+0000) Subject: [AArch64][GlobalISel] Select (variable) shifts. X-Git-Tag: llvmorg-4.0.0-rc1~12329 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2ac5bf94bcaf5617a2f7efcefa2f16755faea8e2;p=platform%2Fupstream%2Fllvm.git [AArch64][GlobalISel] Select (variable) shifts. For now, no support for immediates. llvm-svn: 278804 --- diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index d12c7e1..dad18fd 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -60,6 +60,12 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, return AArch64::ADDWrr; case TargetOpcode::G_SUB: return AArch64::SUBWrr; + case TargetOpcode::G_SHL: + return AArch64::LSLVWr; + case TargetOpcode::G_LSHR: + return AArch64::LSRVWr; + case TargetOpcode::G_ASHR: + return AArch64::ASRVWr; default: return GenericOpc; } @@ -75,6 +81,12 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, return AArch64::ADDXrr; case TargetOpcode::G_SUB: return AArch64::SUBXrr; + case TargetOpcode::G_SHL: + return AArch64::LSLVXr; + case TargetOpcode::G_LSHR: + return AArch64::LSRVXr; + case TargetOpcode::G_ASHR: + return AArch64::ASRVXr; default: return GenericOpc; } @@ -190,6 +202,9 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { case TargetOpcode::G_OR: case TargetOpcode::G_XOR: case TargetOpcode::G_AND: + case TargetOpcode::G_SHL: + case TargetOpcode::G_LSHR: + case TargetOpcode::G_ASHR: case TargetOpcode::G_ADD: case TargetOpcode::G_SUB: { DEBUG(dbgs() << "AArch64: Selecting: binop\n"); diff --git a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp index fc73215..989aeb2 100644 --- a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp @@ -42,6 +42,10 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() { setAction(BinOp, Ty, WidenScalar); } + for (auto BinOp : {G_SHL, G_LSHR, G_ASHR}) + for (auto Ty : {s32, s64}) + setAction(BinOp, Ty, Legal); + for (auto MemOp : {G_LOAD, G_STORE}) for (auto Ty : {s32, s64}) setAction(MemOp, Ty, Legal); diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir index 98b5ccf..fa00874 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir @@ -22,6 +22,15 @@ define void @and_s32_gpr() { ret void } define void @and_s64_gpr() { ret void } + define void @shl_s32_gpr() { ret void } + define void @shl_s64_gpr() { ret void } + + define void @lshr_s32_gpr() { ret void } + define void @lshr_s64_gpr() { ret void } + + define void @ashr_s32_gpr() { ret void } + define void @ashr_s64_gpr() { ret void } + define void @unconditional_br() { ret void } define void @load_s64_gpr(i64* %addr) { ret void } @@ -341,6 +350,186 @@ body: | ... --- +# Same as add_s32_gpr, for G_SHL operations. +# CHECK-LABEL: name: shl_s32_gpr +name: shl_s32_gpr +isSSA: true +legalized: true +regBankSelected: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr32 } +# CHECK-NEXT: - { id: 1, class: gpr32 } +# CHECK-NEXT: - { id: 2, class: gpr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + +# CHECK: body: +# CHECK: %0 = COPY %w0 +# CHECK: %1 = COPY %w1 +# CHECK: %2 = LSLVWr %0, %1 +body: | + bb.0: + liveins: %w0, %w1 + + %0(32) = COPY %w0 + %1(32) = COPY %w1 + %2(32) = G_SHL s32 %0, %1 +... + +--- +# Same as add_s64_gpr, for G_SHL operations. +# CHECK-LABEL: name: shl_s64_gpr +name: shl_s64_gpr +isSSA: true +legalized: true +regBankSelected: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr64 } +# CHECK-NEXT: - { id: 1, class: gpr64 } +# CHECK-NEXT: - { id: 2, class: gpr64 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + +# CHECK: body: +# CHECK: %0 = COPY %x0 +# CHECK: %1 = COPY %x1 +# CHECK: %2 = LSLVXr %0, %1 +body: | + bb.0: + liveins: %x0, %x1 + + %0(64) = COPY %x0 + %1(64) = COPY %x1 + %2(64) = G_SHL s64 %0, %1 +... + +--- +# Same as add_s32_gpr, for G_LSHR operations. +# CHECK-LABEL: name: lshr_s32_gpr +name: lshr_s32_gpr +isSSA: true +legalized: true +regBankSelected: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr32 } +# CHECK-NEXT: - { id: 1, class: gpr32 } +# CHECK-NEXT: - { id: 2, class: gpr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + +# CHECK: body: +# CHECK: %0 = COPY %w0 +# CHECK: %1 = COPY %w1 +# CHECK: %2 = LSRVWr %0, %1 +body: | + bb.0: + liveins: %w0, %w1 + + %0(32) = COPY %w0 + %1(32) = COPY %w1 + %2(32) = G_LSHR s32 %0, %1 +... + +--- +# Same as add_s64_gpr, for G_LSHR operations. +# CHECK-LABEL: name: lshr_s64_gpr +name: lshr_s64_gpr +isSSA: true +legalized: true +regBankSelected: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr64 } +# CHECK-NEXT: - { id: 1, class: gpr64 } +# CHECK-NEXT: - { id: 2, class: gpr64 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + +# CHECK: body: +# CHECK: %0 = COPY %x0 +# CHECK: %1 = COPY %x1 +# CHECK: %2 = LSRVXr %0, %1 +body: | + bb.0: + liveins: %x0, %x1 + + %0(64) = COPY %x0 + %1(64) = COPY %x1 + %2(64) = G_LSHR s64 %0, %1 +... + +--- +# Same as add_s32_gpr, for G_ASHR operations. +# CHECK-LABEL: name: ashr_s32_gpr +name: ashr_s32_gpr +isSSA: true +legalized: true +regBankSelected: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr32 } +# CHECK-NEXT: - { id: 1, class: gpr32 } +# CHECK-NEXT: - { id: 2, class: gpr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + +# CHECK: body: +# CHECK: %0 = COPY %w0 +# CHECK: %1 = COPY %w1 +# CHECK: %2 = ASRVWr %0, %1 +body: | + bb.0: + liveins: %w0, %w1 + + %0(32) = COPY %w0 + %1(32) = COPY %w1 + %2(32) = G_ASHR s32 %0, %1 +... + +--- +# Same as add_s64_gpr, for G_ASHR operations. +# CHECK-LABEL: name: ashr_s64_gpr +name: ashr_s64_gpr +isSSA: true +legalized: true +regBankSelected: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr64 } +# CHECK-NEXT: - { id: 1, class: gpr64 } +# CHECK-NEXT: - { id: 2, class: gpr64 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + +# CHECK: body: +# CHECK: %0 = COPY %x0 +# CHECK: %1 = COPY %x1 +# CHECK: %2 = ASRVXr %0, %1 +body: | + bb.0: + liveins: %x0, %x1 + + %0(64) = COPY %x0 + %1(64) = COPY %x1 + %2(64) = G_ASHR s64 %0, %1 +... + +--- # CHECK-LABEL: name: unconditional_br name: unconditional_br isSSA: true