From: Anson Huang Date: Mon, 1 Jun 2020 10:37:44 +0000 (+0800) Subject: dt-bindings: mailbox: Convert imx mu to json-schema X-Git-Tag: v5.15~3587^2~3 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2a975ac9c30c938ee6d4131988045dabca9c7367;p=platform%2Fkernel%2Flinux-starfive.git dt-bindings: mailbox: Convert imx mu to json-schema Convert the i.MX MU binding to DT schema format using json-schema Signed-off-by: Anson Huang Signed-off-by: Rob Herring --- diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt deleted file mode 100644 index 26b7a88..0000000 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt +++ /dev/null @@ -1,58 +0,0 @@ -NXP i.MX Messaging Unit (MU) --------------------------------------------------------------------- - -The Messaging Unit module enables two processors within the SoC to -communicate and coordinate by passing messages (e.g. data, status -and control) through the MU interface. The MU also provides the ability -for one processor to signal the other processor using interrupts. - -Because the MU manages the messaging between processors, the MU uses -different clocks (from each side of the different peripheral buses). -Therefore, the MU must synchronize the accesses from one side to the -other. The MU accomplishes synchronization using two sets of matching -registers (Processor A-facing, Processor B-facing). - -Messaging Unit Device Node: -============================= - -Required properties: -------------------- -- compatible : should be "fsl,-mu", the supported chips include - imx6sx, imx7s, imx8qxp, imx8qm. - The "fsl,imx6sx-mu" compatible is seen as generic and should - be included together with SoC specific compatible. - There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu" - compatible to support it. - To communicate with i.MX8 SCU, "fsl,imx8-mu-scu" could be - used for fast IPC -- reg : Should contain the registers location and length -- interrupts : Interrupt number. The interrupt specifier format depends - on the interrupt controller parent. -- #mbox-cells: Must be 2. - <&phandle type channel> - phandle : Label name of controller - type : Channel type - channel : Channel number - - This MU support 4 type of unidirectional channels, each type - has 4 channels. A total of 16 channels. Following types are - supported: - 0 - TX channel with 32bit transmit register and IRQ transmit - acknowledgment support. - 1 - RX channel with 32bit receive register and IRQ support - 2 - TX doorbell channel. Without own register and no ACK support. - 3 - RX doorbell channel. - -Optional properties: -------------------- -- clocks : phandle to the input clock. -- fsl,mu-side-b : Should be set for side B MU. - -Examples: --------- -lsio_mu0: mailbox@5d1b0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x0 0x5d1b0000 0x0 0x10000>; - interrupts = ; - #mbox-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml new file mode 100644 index 0000000..3b35eb5 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX Messaging Unit (MU) + +maintainers: + - Dong Aisheng + +description: | + The Messaging Unit module enables two processors within the SoC to + communicate and coordinate by passing messages (e.g. data, status + and control) through the MU interface. The MU also provides the ability + for one processor to signal the other processor using interrupts. + + Because the MU manages the messaging between processors, the MU uses + different clocks (from each side of the different peripheral buses). + Therefore, the MU must synchronize the accesses from one side to the + other. The MU accomplishes synchronization using two sets of matching + registers (Processor A-facing, Processor B-facing). + +properties: + compatible: + oneOf: + - const: fsl,imx6sx-mu + - const: fsl,imx7ulp-mu + - const: fsl,imx8-mu-scu + - items: + - enum: + - fsl,imx7s-mu + - fsl,imx8mq-mu + - fsl,imx8mm-mu + - fsl,imx8mn-mu + - fsl,imx8mp-mu + - fsl,imx8qxp-mu + - const: fsl,imx6sx-mu + - description: To communicate with i.MX8 SCU with fast IPC + items: + - const: fsl,imx8qxp-mu + - const: fsl,imx8-mu-scu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#mbox-cells": + description: | + <&phandle type channel> + phandle : Label name of controller + type : Channel type + channel : Channel number + + This MU support 4 type of unidirectional channels, each type + has 4 channels. A total of 16 channels. Following types are + supported: + 0 - TX channel with 32bit transmit register and IRQ transmit + acknowledgment support. + 1 - RX channel with 32bit receive register and IRQ support + 2 - TX doorbell channel. Without own register and no ACK support. + 3 - RX doorbell channel. + const: 2 + + clocks: + maxItems: 1 + + fsl,mu-side-b: + description: boolean, if present, means it is for side B MU. + type: boolean + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + + mailbox@5d1b0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d1b0000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + };