From: Vladislav Dzhidzhoev <vdzhidzhoev@accesssoftek.com>
Date: Fri, 27 Jan 2023 02:01:22 +0000 (+0100)
Subject: [GlobalISel] Don't combine instructions with unknown type in hoist_logic_op_with_same... 
X-Git-Tag: upstream/17.0.6~18991
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2a45d061ef81e9af7f61193691b1537b99898494;p=platform%2Fupstream%2Fllvm.git

[GlobalISel] Don't combine instructions with unknown type in hoist_logic_op_with_same_opcode_hands.

This fixes failure for some LLVM IR.

Differential Revision: https://reviews.llvm.org/D142791
---

diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index bbb7c7c..7b85f2e 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -2750,7 +2750,7 @@ bool CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(
   Register Y = RightHandInst->getOperand(1).getReg();
   LLT XTy = MRI.getType(X);
   LLT YTy = MRI.getType(Y);
-  if (XTy != YTy)
+  if (!XTy.isValid() || XTy != YTy)
     return false;
   if (!isLegalOrBeforeLegalizer({LogicOpcode, {XTy, YTy}}))
     return false;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir
index b05bd92..0c624d7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir
@@ -58,3 +58,20 @@ body:             |
     %logic_op:_(s64) = G_OR %hand1, %hand2
     $x0 = COPY %logic_op(s64)
     RET_ReallyLR implicit $x0
+
+...
+---
+name:            dont_combine_physreg
+tracksRegLiveness: true
+legalized: true
+body:             |
+  bb.0:
+    liveins: $w0, $w1
+    ; Post-legalization, we must not crash here.
+    ;
+    ; CHECK-LABEL: name: dont_combine_physreg
+    %x:_(s32) = COPY $w0
+    %y:_(s32) = COPY $w1
+    %logic_op:_(s32) = G_OR %x, %y
+    $w0 = COPY %logic_op(s32)
+    RET_ReallyLR implicit $w0