From: Geert Uytterhoeven Date: Mon, 21 Feb 2022 16:25:20 +0000 (+0100) Subject: clk: renesas: rzg2l: Simplify multiplication/shift logic X-Git-Tag: v6.1-rc5~1232^2~3^5~1^2~7 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=29db30c45f07c929c86c40a5b85f18b69c89c638;p=platform%2Fkernel%2Flinux-starfive.git clk: renesas: rzg2l: Simplify multiplication/shift logic "a * (1 << b)" == "a << b". No change in generated code. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/71e1cf2e30fb2d7966fc8ec6bab23eb7e24aa1c4.1645460687.git.geert+renesas@glider.be --- diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index b3a1533..f626d27 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -289,7 +289,7 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw, val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf)); mult = MDIV(val1) + KDIV(val1) / 65536; - div = PDIV(val1) * (1 << SDIV(val2)); + div = PDIV(val1) << SDIV(val2); return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div); }