From: Palmer Dabbelt <palmer@rivosinc.com>
Date: Thu, 2 Jun 2022 01:34:02 +0000 (-0700)
Subject: RISC-V: PolarFire SoC Device Tree Updates
X-Git-Tag: v6.1-rc5~1154^2~10
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2981deb83de2b94947086a992b961b2339988a71;p=platform%2Fkernel%2Flinux-starfive.git

RISC-V: PolarFire SoC Device Tree Updates

This add a device tree for Sundance Polarberry, along with various
cleanups to the PolarFire SOC device trees and bindings.

Link: https://lore.kernel.org/r/20220509142610.128590-1-conor.dooley@microchip.com

* 'riscv-pfsoc-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/palmer/linux:
  riscv: dts: icicle: sort nodes alphabetically
  riscv: microchip: icicle: readability fixes
  riscv: dts: microchip: add the sundance polarberry
  dt-bindings: riscv: microchip: add polarberry compatible string
  dt-bindings: vendor-prefixes: add Sundance DSP
  riscv: dts: microchip: make the fabric dtsi board specific
  dt-bindings: riscv: microchip: document icicle reference design
  riscv: dts: microchip: remove soc vendor from filenames
  riscv: dts: microchip: move sysctrlr out of soc bus
  riscv: dts: microchip: remove icicle memory clocks
---

2981deb83de2b94947086a992b961b2339988a71