From: Hao Liu Date: Sun, 28 Sep 2014 23:50:06 +0000 (+0200) Subject: clocksource: sirf: Disable counter before re-setting it X-Git-Tag: v5.15~17108^2~4 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=28cf35675a66947b20731f6acbc9d5b131930ce3;p=platform%2Fkernel%2Flinux-starfive.git clocksource: sirf: Disable counter before re-setting it According to HW spec, we have to disable the counter before setting it, if we don't this, in pressure test, sometimes the timer might not generate interrupt any more. And this patch also fixes a typo for register set by changing 0x7 to 0x3. 0x7 is loop mode in HW, but here we are using oneshot 0x3. Signed-off-by: Hao Liu Signed-off-by: Barry Song Signed-off-by: Daniel Lezcano --- diff --git a/drivers/clocksource/timer-marco.c b/drivers/clocksource/timer-marco.c index 330e930..caf7a20 100644 --- a/drivers/clocksource/timer-marco.c +++ b/drivers/clocksource/timer-marco.c @@ -63,7 +63,7 @@ static inline void sirfsoc_timer_count_disable(int idx) /* enable count and interrupt */ static inline void sirfsoc_timer_count_enable(int idx) { - writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7, + writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx); } @@ -103,6 +103,9 @@ static int sirfsoc_timer_set_next_event(unsigned long delta, { int cpu = smp_processor_id(); + /* disable timer first, then modify the related registers */ + sirfsoc_timer_count_disable(cpu); + writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 + 4 * cpu); writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +