From: Haojian Zhuang Date: Wed, 2 Apr 2014 13:31:50 +0000 (+0800) Subject: ARM: dts: fix L2 address in Hi3620 X-Git-Tag: v4.9.8~6014^2~3 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=28c9770bcbd2b6dbab99669825a2f8fa69e6d35b;p=platform%2Fkernel%2Flinux-rpi3.git ARM: dts: fix L2 address in Hi3620 Fix the address of L2 controler register in hi3620 SoC. This has been wrong from the point that the file was merged in v3.14. Signed-off-by: Haojian Zhuang Acked-by: Wei Xu Cc: stable@vger.kernel.org Signed-off-by: Arnd Bergmann --- diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index ab1116d..83a5b86 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -73,7 +73,7 @@ L2: l2-cache { compatible = "arm,pl310-cache"; - reg = <0xfc10000 0x100000>; + reg = <0x100000 0x100000>; interrupts = <0 15 4>; cache-unified; cache-level = <2>;