From: Kazu Hirata Date: Thu, 4 Nov 2021 15:51:05 +0000 (-0700) Subject: [Hexagon] Use make_early_inc_range (NFC) X-Git-Tag: upstream/15.0.7~26728 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2887117d2c5748ba9efeb588d9bc1e4a73b674ff;p=platform%2Fupstream%2Fllvm.git [Hexagon] Use make_early_inc_range (NFC) --- diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp index 3660fa4..8dc26ba 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -3132,11 +3132,9 @@ void HexagonConstEvaluator::replaceAllRegUsesWith(Register FromReg, Register ToReg) { assert(FromReg.isVirtual()); assert(ToReg.isVirtual()); - for (auto I = MRI->use_begin(FromReg), E = MRI->use_end(); I != E;) { - MachineOperand &O = *I; - ++I; + for (MachineOperand &O : + llvm::make_early_inc_range(MRI->use_operands(FromReg))) O.setReg(ToReg); - } } bool HexagonConstEvaluator::rewriteHexBranch(MachineInstr &BrI, diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp index fcc8804..c444cf5 100644 --- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -1070,20 +1070,18 @@ bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond, bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B, std::set &UpdRegs) { bool Changed = false; - MachineBasicBlock::iterator I, E, NextI; - for (I = B.begin(), E = B.end(); I != E; I = NextI) { - NextI = std::next(I); - unsigned Opc = I->getOpcode(); + for (MachineInstr &MI : llvm::make_early_inc_range(B)) { + unsigned Opc = MI.getOpcode(); if (Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf) { - bool Done = predicate(*I, (Opc == Hexagon::A2_tfrt), UpdRegs); + bool Done = predicate(MI, (Opc == Hexagon::A2_tfrt), UpdRegs); if (!Done) { // If we didn't predicate I, we may need to remove it in case it is // an "identity" copy, e.g. %1 = A2_tfrt %2, %1. - if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) { - for (auto &Op : I->operands()) + if (RegisterRef(MI.getOperand(0)) == RegisterRef(MI.getOperand(2))) { + for (auto &Op : MI.operands()) if (Op.isReg()) UpdRegs.insert(Op.getReg()); - removeInstr(*I); + removeInstr(MI); } } Changed |= Done; diff --git a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp index 07f85e6..8120a61 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp @@ -232,22 +232,19 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) { CondsetMap CM; MuxInfoList ML; - MachineBasicBlock::iterator NextI, End = B.end(); - for (MachineBasicBlock::iterator I = B.begin(); I != End; I = NextI) { - MachineInstr *MI = &*I; - NextI = std::next(I); - unsigned Opc = MI->getOpcode(); + for (MachineInstr &MI : llvm::make_early_inc_range(B)) { + unsigned Opc = MI.getOpcode(); if (!isCondTransfer(Opc)) continue; - Register DR = MI->getOperand(0).getReg(); + Register DR = MI.getOperand(0).getReg(); if (isRegPair(DR)) continue; - MachineOperand &PredOp = MI->getOperand(1); + MachineOperand &PredOp = MI.getOperand(1); if (PredOp.isUndef()) continue; Register PR = PredOp.getReg(); - unsigned Idx = I2X.lookup(MI); + unsigned Idx = I2X.lookup(&MI); CondsetMap::iterator F = CM.find(DR); bool IfTrue = HII->isPredicatedTrue(Opc); diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index 78e4eea..a4971ad 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -1094,15 +1094,15 @@ void HexagonHardwareLoops::removeIfDead(MachineInstr *MI) { if (!MO.isReg() || !MO.isDef()) continue; Register Reg = MO.getReg(); - MachineRegisterInfo::use_iterator nextI; - for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg), - E = MRI->use_end(); I != E; I = nextI) { - nextI = std::next(I); // I is invalidated by the setReg - MachineInstr *UseMI = I->getParent(); + // We use make_early_inc_range here because setReg below invalidates the + // iterator. + for (MachineOperand &MO : + llvm::make_early_inc_range(MRI->use_operands(Reg))) { + MachineInstr *UseMI = MO.getParent(); if (UseMI == MI) continue; - if (I->isDebug()) - I->setReg(0U); + if (MO.isDebug()) + MO.setReg(0U); } } diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index d1c6f61..2679e39 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -2247,8 +2247,8 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { } void HexagonDAGToDAGISel::rebalanceAddressTrees() { - for (auto I = CurDAG->allnodes_begin(), E = CurDAG->allnodes_end(); I != E;) { - SDNode *N = &*I++; + for (SDNode &Node : llvm::make_early_inc_range(CurDAG->allnodes())) { + SDNode *N = &Node; if (N->getOpcode() != ISD::LOAD && N->getOpcode() != ISD::STORE) continue; diff --git a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp index 8ddd52d..0452248 100644 --- a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp +++ b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp @@ -1490,10 +1490,8 @@ void PolynomialMultiplyRecognize::cleanupLoopBody(BasicBlock *LoopB) { if (Value *SV = SimplifyInstruction(&I, {DL, &TLI, &DT})) I.replaceAllUsesWith(SV); - for (auto I = LoopB->begin(), N = I; I != LoopB->end(); I = N) { - N = std::next(I); - RecursivelyDeleteTriviallyDeadInstructions(&*I, &TLI); - } + for (Instruction &I : llvm::make_early_inc_range(*LoopB)) + RecursivelyDeleteTriviallyDeadInstructions(&I, &TLI); } unsigned PolynomialMultiplyRecognize::getInverseMxN(unsigned QP) { diff --git a/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp b/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp index f9fb14c..4890c3d 100644 --- a/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp @@ -70,9 +70,7 @@ bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) { // Loop over all of the basic blocks for (MachineBasicBlock &B : Fn) { - for (auto I = B.begin(), E = B.end(); I != E; ) { - MachineInstr &MI = *I; - ++I; + for (MachineInstr &MI : llvm::make_early_inc_range(B)) { unsigned Opc = MI.getOpcode(); if (Opc == Hexagon::CONST32) { diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 191aef7..cb73f43 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -1160,12 +1160,9 @@ bool HexagonPacketizerList::cannotCoexist(const MachineInstr &MI, void HexagonPacketizerList::unpacketizeSoloInstrs(MachineFunction &MF) { for (auto &B : MF) { MachineBasicBlock::iterator BundleIt; - MachineBasicBlock::instr_iterator NextI; - for (auto I = B.instr_begin(), E = B.instr_end(); I != E; I = NextI) { - NextI = std::next(I); - MachineInstr &MI = *I; + for (MachineInstr &MI : llvm::make_early_inc_range(B.instrs())) { if (MI.isBundle()) - BundleIt = I; + BundleIt = MI.getIterator(); if (!MI.isInsideBundle()) continue;