From: Hal Finkel <hfinkel@anl.gov>
Date: Fri, 2 Sep 2016 23:42:01 +0000 (+0000)
Subject: [PowerPC] Add asm parser/disassembler support for hrfid,nap,slbmfev
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=28842b96f3c30f34486d9feb32693e2ec2dc37ca;p=platform%2Fupstream%2Fllvm.git

[PowerPC] Add asm parser/disassembler support for hrfid,nap,slbmfev

These few book-III instructions are used by the Linux kernel.

Partially fixes PR24796.

llvm-svn: 280560
---

diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index 5acff75..dfbf806 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -1193,6 +1193,25 @@ class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
   let Inst{31}    = 0;
 }
 
+class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+                  InstrItinClass itin, list<dag> pattern>
+  : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+  let CRD = 0;
+  let CRA = 0;
+  let CRB = 0;
+}
+
+class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+                   InstrItinClass itin, list<dag> pattern>
+  : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+  bits<5> RT;
+  bits<5> RB;
+
+  let CRD = RT;
+  let CRA = 0;
+  let CRB = RB;
+}
+
 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
     : I<opcode, OOL, IOL, asmstr, itin> {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index a3e85dd..4edfe94 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3697,6 +3697,9 @@ def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
                        "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
 
+def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB),
+                       "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>;
+
 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
 
 def TLBIA : XForm_0<31, 370, (outs), (ins),
@@ -3759,6 +3762,9 @@ def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
                       "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
 
+def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>;
+def NAP   : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>;
+
 def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
 
 def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
diff --git a/llvm/lib/Target/PowerPC/PPCSchedule.td b/llvm/lib/Target/PowerPC/PPCSchedule.td
index b4d72ef..a1eac32 100644
--- a/llvm/lib/Target/PowerPC/PPCSchedule.td
+++ b/llvm/lib/Target/PowerPC/PPCSchedule.td
@@ -109,6 +109,7 @@ def IIC_SprSLBIE     : InstrItinClass;
 def IIC_SprSLBIEG    : InstrItinClass;
 def IIC_SprSLBMTE    : InstrItinClass;
 def IIC_SprSLBMFEE   : InstrItinClass;
+def IIC_SprSLBMFEV   : InstrItinClass;
 def IIC_SprSLBIA     : InstrItinClass;
 def IIC_SprSLBSYNC   : InstrItinClass;
 def IIC_SprTLBIA     : InstrItinClass;
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt
index 04308f9..8602a3d 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt
@@ -1,5 +1,11 @@
 # RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s
 
+# CHECK: hrfid
+0x4c 0x00 0x02 0x24
+
+# CHECK: nap
+0x4c 0x00 0x03 0x64
+
 # CHECK: mtmsr 4
 0x7c 0x80 0x01 0x24
 
@@ -90,6 +96,9 @@
 # CHECK: slbmfee 4, 5                    
 0x7c 0x80 0x2f 0x26
 
+0x7c 0x40 0x1e 0xa6
+# CHECK: slbmfev 2, 3
+
 # CHECK: slbia                           
 0x7c 0x00 0x03 0xe4
 
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s b/llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s
index d110d4ab..d157ea0 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s
@@ -1,6 +1,14 @@
 # RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
 # RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
 
+# CHECK-BE: hrfid                            # encoding: [0x4c,0x00,0x02,0x24]
+# CHECK-LE: hrfid                            # encoding: [0x24,0x02,0x00,0x4c]
+            hrfid
+
+# CHECK-BE: nap                              # encoding: [0x4c,0x00,0x03,0x64]
+# CHECK-LE: nap                              # encoding: [0x64,0x03,0x00,0x4c]
+            nap   
+
 # CHECK-BE: mtmsr 4                          # encoding: [0x7c,0x80,0x01,0x24]
 # CHECK-LE: mtmsr 4                          # encoding: [0x24,0x01,0x80,0x7c]
             mtmsr %r4
@@ -134,6 +142,10 @@
 # CHECK-LE: slbmfee 4, 5                    # encoding: [0x26,0x2f,0x80,0x7c]
             slbmfee %r4, %r5
 
+# CHECK-BE: slbmfev 2, 3                    # encoding: [0x7c,0x40,0x1e,0xa6]
+# CHECK-LE: slbmfev 2, 3                    # encoding: [0xa6,0x1e,0x40,0x7c]
+            slbmfev %r2, %r3
+
 # CHECK-BE: slbia                           # encoding: [0x7c,0x00,0x03,0xe4]
 # CHECK-LE: slbia                           # encoding: [0xe4,0x03,0x00,0x7c]
             slbia