From: Jason Gunthorpe Date: Tue, 26 Nov 2013 18:02:52 +0000 (-0700) Subject: PCI: mvebu: Drop writes to bridge Secondary Status register X-Git-Tag: v3.14-rc1~132^2~10^2~6 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2850b05c9644d0f4c9df6cc77d628d7e0598a0cc;p=kernel%2Fkernel-generic.git PCI: mvebu: Drop writes to bridge Secondary Status register There are no writable bits in the secondary status register, only RO and RW1C (write-1-to-clear) bits. The driver never sets any of the RW1C bits, so the status register should always be 0, just remove the set from the write path. Someday the RW1C bits should be copied/cleared directly from registers in the HW. [bhelgaas: changelog tweaks] Signed-off-by: Jason Gunthorpe Signed-off-by: Bjorn Helgaas Acked-by: Jason Cooper --- diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c index c269e43..6f5a20f 100644 --- a/drivers/pci/host/pci-mvebu.c +++ b/drivers/pci/host/pci-mvebu.c @@ -500,7 +500,6 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, */ bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32; bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32; - bridge->secondary_status = value >> 16; mvebu_pcie_handle_iobase_change(port); break;