From: Krzysztof Parzyszek Date: Sat, 5 Nov 2016 21:44:50 +0000 (+0000) Subject: [Hexagon] Relocate pattern-related bits to proper places X-Git-Tag: llvmorg-4.0.0-rc1~5417 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2839b29f4b911f6fcbbc4ca2a81c6dc4a4655cd4;p=platform%2Fupstream%2Fllvm.git [Hexagon] Relocate pattern-related bits to proper places llvm-svn: 286049 --- diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index c44e931..50cb311 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -186,6 +186,7 @@ private: bool isValueExtension(const SDValue &Val, unsigned FromBits, SDValue &Src); bool orIsAdd(const SDNode *N) const; bool isAlignedMemNode(const MemSDNode *N) const; + bool isPositiveHalfWord(const SDNode *N) const; SmallDenseMap RootWeights; SmallDenseMap RootHeights; @@ -1538,6 +1539,19 @@ bool HexagonDAGToDAGISel::isAlignedMemNode(const MemSDNode *N) const { return N->getAlignment() >= N->getMemoryVT().getStoreSize(); } +// Return true when the given node fits in a positive half word. +bool HexagonDAGToDAGISel::isPositiveHalfWord(const SDNode *N) const { + if (const ConstantSDNode *CN = dyn_cast(N)) { + int64_t V = CN->getSExtValue(); + return V > 0 && isInt<16>(V); + } + if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) { + const VTSDNode *VN = dyn_cast(N->getOperand(1)); + return VN->getVT().getSizeInBits() <= 16; + } + return false; +} + //////////////////////////////////////////////////////////////////////////////// // Rebalancing of address calculation trees diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 785084c..0a8b935 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -3201,20 +3201,6 @@ EVT HexagonTargetLowering::getOptimalMemOpType(uint64_t Size, return MVT::Other; } -// Return true when the given node fits in a positive half word. -bool llvm::isPositiveHalfWord(SDNode *N) { - ConstantSDNode *CN = dyn_cast(N); - if (CN && CN->getSExtValue() > 0 && isInt<16>(CN->getSExtValue())) - return true; - - switch (N->getOpcode()) { - default: - return false; - case ISD::SIGN_EXTEND_INREG: - return true; - } -} - bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *Fast) const { if (Fast) diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index cd8df8a..3d0fcdf 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -21,10 +21,6 @@ #include "llvm/Target/TargetLowering.h" namespace llvm { - -// Return true when the given node fits in a positive half word. -bool isPositiveHalfWord(SDNode *N); - namespace HexagonISD { enum NodeType : unsigned { OP_BEGIN = ISD::BUILTIN_OP_END, diff --git a/llvm/lib/Target/Hexagon/HexagonOperands.td b/llvm/lib/Target/Hexagon/HexagonOperands.td index 7ded7ed..559a488 100644 --- a/llvm/lib/Target/Hexagon/HexagonOperands.td +++ b/llvm/lib/Target/Hexagon/HexagonOperands.td @@ -258,25 +258,6 @@ def nOneImmPred : PatLeaf<(i32 imm), [{ return (-1 == v); }]>; -def Set5ImmPred : PatLeaf<(i32 imm), [{ - // Set5ImmPred predicate - True if the number is in the series of values. - // [ 2^0, 2^1, ... 2^31 ] - // For use in setbit immediate. - uint32_t v = (int32_t)N->getSExtValue(); - // Constrain to 32 bits, and then check for single bit. - return ImmIsSingleBit(v); -}]>; - -def Clr5ImmPred : PatLeaf<(i32 imm), [{ - // Clr5ImmPred predicate - True if the number is in the series of - // bit negated values. - // [ 2^0, 2^1, ... 2^31 ] - // For use in clrbit immediate. - // Note: we are bit NOTing the value. - uint32_t v = ~ (int32_t)N->getSExtValue(); - // Constrain to 32 bits, and then check for single bit. - return ImmIsSingleBit(v); -}]>; // Extendable immediate operands. def f32ExtOperand : AsmOperandClass { let Name = "f32Ext"; } @@ -394,12 +375,3 @@ def calltarget : Operand { def bblabel : Operand; def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf, [], "BasicBlockSDNode">; - -// Return true if for a 32 to 64-bit sign-extended load. -def is_sext_i32 : PatLeaf<(i64 DoubleRegs:$src1), [{ - LoadSDNode *LD = dyn_cast(N); - if (!LD) - return false; - return LD->getExtensionType() == ISD::SEXTLOAD && - LD->getMemoryVT().getScalarType() == MVT::i32; -}]>; diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td index fe702a4..b242c55 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatterns.td +++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td @@ -19,6 +19,26 @@ def HiReg: OutPatFrag<(ops node:$Rs), def orisadd: PatFrag<(ops node:$Addr, node:$off), (or node:$Addr, node:$off), [{ return orIsAdd(N); }]>; +def Set5ImmPred : PatLeaf<(i32 imm), [{ + // Set5ImmPred predicate - True if the number is in the series of values. + // [ 2^0, 2^1, ... 2^31 ] + // For use in setbit immediate. + uint32_t v = N->getZExtValue(); + // Constrain to 32 bits, and then check for single bit. + return isPowerOf2_32(v); +}]>; + +def Clr5ImmPred : PatLeaf<(i32 imm), [{ + // Clr5ImmPred predicate - True if the number is in the series of + // bit negated values. + // [ 2^0, 2^1, ... 2^31 ] + // For use in clrbit immediate. + // Note: we are bit NOTing the value. + uint32_t v = ~N->getZExtValue(); + // Constrain to 32 bits, and then check for single bit. + return isPowerOf2_32(v); +}]>; + // SDNode for converting immediate C to C-1. def DEC_CONST_SIGNED : SDNodeXForm; } +def PositiveHalfWord : PatLeaf<(i32 IntRegs:$a), [{ + return isPositiveHalfWord(N); +}]>; multiclass MinMax_pats { defm: T_MinMax_pats; @@ -336,16 +359,24 @@ def: T_MType_acc_pat3 ; def: T_MType_acc_pat3 ; def: T_MType_acc_pat3 ; -def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))), - (i64 (anyext (i32 IntRegs:$src2))))), +// Return true if for a 32 to 64-bit sign-extended load. +def Sext64Ld : PatLeaf<(i64 DoubleRegs:$src1), [{ + LoadSDNode *LD = dyn_cast(N); + if (!LD) + return false; + return LD->getExtensionType() == ISD::SEXTLOAD && + LD->getMemoryVT().getScalarType() == MVT::i32; +}]>; + +def: Pat<(i64 (mul (i64 (anyext I32:$src1)), + (i64 (anyext I32:$src2)))), (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>; -def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))), - (i64 (sext (i32 IntRegs:$src2))))), +def: Pat<(i64 (mul (i64 (sext I32:$src1)), + (i64 (sext I32:$src2)))), (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>; -def: Pat<(i64 (mul (is_sext_i32:$src1), - (is_sext_i32:$src2))), +def: Pat<(i64 (mul Sext64Ld:$src1, Sext64Ld:$src2)), (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>; // Multiply and accumulate, use full result. diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td index c88c033..aa0cca0 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -282,8 +282,3 @@ def VolatileV3 { W12, W13, W14, W15, Q0, Q1, Q2, Q3]; } - -def PositiveHalfWord : PatLeaf<(i32 IntRegs:$a), -[{ - return isPositiveHalfWord(N); -}]>;